OTHER

· Read/Write Cycle Times

17 ns (Typical)

25 ns (-55 to 125

· Typical Operating Power <10 mW/MHz

· Asynchronous Operation

· JEDEC Standard Low Voltage

CMOS Compatible I/O

· Single 3.3 V

0.3V Power Supply

· Packaging Options

- 28-Lead Flat Pack (0.500 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- Various Multi-Chip Module (MCM) Configurations

32K x 8 STATIC RAM--Low Power SOI

HLX6256

Military & Space Products

RADIATION

· Fabricated with RICMOS

IV Silicon on Insulator (SOI)

0.55

m Low Power Process

· Total Dose Hardness through 1x10

rad(SiO

)

· Neutron Hardness through 1x10

-2

· Dynamic and Static Transient Upset Hardness

through 1x10

rad(Si)/s

· Dose Rate Survivability through 1x10

rad(Si)/s

· Soft Error Rate of <1x10

-10

upsets/bit-day

· Latchup Free

GENERAL DESCRIPTION

The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 word x 8-bit static random access
memory with industry-standard functionality. It is fabri-
cated with Honeywell's radiation hardened technology,
and is designed for use in low voltage systems operating in
radiation environments. The RAM operates over the full
military temperature range and requires only a single 3.3 V

0.3V power supply. The RAM is compatible with JEDEC

standard low voltage CMOS I/O. Power consumption is
typically less than 10 mW/MHz in operation, and less than
2 mW when de-selected. The RAM read operation is fully
asynchronous, with an associated typical access time of 14
ns at 3.3 V.

Honeywell's enhanced SOI RICMOS

IV (Radiation Insen-

sitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and pro-
cess hardening techniques. The RICMOS

IV low power

process is a SIMOX CMOS technology with a 150 Å gate
oxide and a minimum drawn feature size of 0.7

m (0.55

effective gate length--L

eff

). Additional features include

tungsten via plugs, Honeywell's proprietary SHARP pla-
narization process and a lightly doped drain (LDD) struc-
ture for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.

FEATURES

HLX6256

*Not Available in 28-Lead DIP or 28-Lead Flat Pack

SIGNAL DEFINITIONS

A: 0-14

Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7

Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.

NCS

Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.

NWE

Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.

NOE

Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.

CE*

Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.

NCS

CE*

NWE

NOE

MODE

Read

Data Out

Write

Data In

Deselected

High Z

Disabled

High Z

TRUTH TABLE

FUNCTIONAL DIAGRAM

Notes:

X: VI=VIH or VIL

XX: VSS

VDD

NOE=H: High Z output state maintained for

NCS=X, CE=X, NWE=X

NCS

A:0-8,12-13

NWE

NOE

WE · CS · CE

NWE · CS · CE · OE

Column Decoder
Data Input/Output

Row
Decoder

32,768 x 8

Memory

Array

A:9-11, 14

Signal

All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)

1 = enabled

Signal

DQ:0-7

(0 = high Z)

·
·
·

· · ·

HLX6256

Total Dose

1x10

rad(SiO

)

Transient Dose Rate Upset (3)

1x10

rad(Si)/s

Transient Dose Rate Survivability (3)

1x10

rad(Si)/s

Soft Error Rate (SER)

<1x10

-10

upsets/bit-day

Neutron Fluence

1x10

N/cm

Parameter

Limits (2)

Test Conditions

RADIATION HARDNESS RATINGS (1)

Units

=25

Total Ionizing Radiation Dose

The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 3.6 V and T =125

extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transis-
tors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 keV X-rays applied at a
dose rate of 1x10

rad(SiO

)/min at T = 25

C and gamma

rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.

Transient Pulse Ionizing Radiation

The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate upset
specification, when applied under recommended operat-
ing conditions. To ensure validity of all specified perfor-
mance parameters before, during, and after radiation
(timing degradation during transient pulse radiation (tim-
ing degradation during transient pulse radiation is

10%),

it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum induc-
tance between the package (chip) and stiffening capaci-
tance of 0.7 nH per part. If there are no operate-through
or valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.

(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55

C to 125

(3) Not guaranteed with 28Lead DIP.

1 MeV equivalent energy,
Unbiased, T

=25

=125

C, Adams 10%

worst case environment

Pulse width

50 ns, X-ray,

VDD=4.0 V, T

=25

Pulse width

The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse of up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs and
power supply may significantly exceed the normal operat-
ing levels. The application design must accommodate
these effects.

Neutron Radiation

The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.

Soft Error Rate

The SRAM is immune to single event upsets (SEU's) to the
specified soft error rate (SER), under recommended oper-
ating conditions. This hardness level is defined by the
Adams 10% worst case cosmic ray environment for geo-
synchronous orbits.

Latchup

The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the SIMOX
substrate material provides oxide isolation between adja-
cent PMOS and NMOS transistors and eliminates any
potential SCR latchup structures. Sufficient transistor
body tie connections to the p- and n-channel substrates
are made to ensure no source/drain snapback occurs.

RADIATION CHARACTERISTICS

HLX6256

VDD

Positive Supply Voltage (2)

-0.5

6.5

VPIN

Voltage on Any Pin (2)

-0.5

VDD+0.5

TSTORE

Storage Temperature (Zero Bias)

-65

150

TSOLDER

Soldering Temperature · Time

270·5

C·s

Total Package Power Dissipation (3)

2.0

IOUT

DC or Average Output Current

2.0

VPROT

ESD Input Protection Voltage (4)

2000

28 FP/36 FP

28 DIP

Junction Temperature

175

Parameter

Symbol

Parameter

Max

Symbol

Test Conditions

Worst Case

Units

CAPACITANCE (1)

Symbol

Test Conditions

Min

Max

Typical

(1)

Units

VDR

Data Retention Voltage

1.65

IDR

Data Retention Current

300

Thermal Resistance (Jct-to-Case)

(1) This parameter is tested during initial design characterization only.

RECOMMENDED OPERATING CONDITIONS

Symbol

Max

Typ

Description

Parameter

Min

Worst Case

(2)

C/W

Units

VDD

Supply Voltage (referenced to VSS)

3.0

3.3

3.6

Ambient Temperature

-55

125

VPIN

Voltage on Any Pin (referenced to VSS)

-0.3

VDD+0.3

Min

Typical

(1)

Input Capacitance

VI=VDD or VSS, f=1 MHz

Output Capacitance

VIO=VDD or VSS, f=1 MHz

Units

Rating

Min

Max

(1) Typical operating conditions: TA= 25

C, pre-radiation.

(2) Worst case operating conditions: TA= -55

C to +125

C, post total dose at 25

DATA RETENTION CHARACTERISTICS

Parameter

(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not

implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.

(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.

ABSOLUTE MAXIMUM RATINGS (1)

NCS=VDD=VDR

VI=VDR or VSS

NCS=VDR

VI=VDR or VSS

HLX6256

IDDSB1

Static Supply Current

1.0

IDDSBMF Standby Supply Current - Deselected

1.0

IDDOPW

Dynamic Supply Current, Selected

(Write)

3.0

IDDOPR

Dynamic Supply Current, Selected

(Read)

3.0

Input Leakage Current

-1

IOZ

Output Leakage Current

-1

VIL

Low-Level Input Voltage

VIH

High-Level Input Voltage

DC ELECTRICAL CHARACTERISTICS

Units

Test Conditions

Min

Max

Worst Case (2)

Symbol

Parameter

Typical

(1)

NCS=VDD, IO=0,

f=40 MHz

VIH=VDD IO=0

VIL=VSS Inputs Stable

f=1 MHz, IO=0, CE=VIH=VDD

NCS=VIL=VSS

f=1 MHz, IO=0, CE=VIH=VDD

NCS=VIL=VSS

VSS

VDD

VSS

VIO

VDD

Output=high Z

0.7xV

+.3

March Pattern

VDD = 3.6V

0.4

VDD = 3.0V, IOL = 8 mA

2.7

VDD = 3.0V, IOH = -4 mA

-0.3

0.3xV

March Pattern

VDD = 3.0V

VOL

Low-Level Output Voltage

VOH

High-Level Output Voltage

(1) Typical operating conditions: VDD=3.3 V, TA=25

C, pre-radiation.

(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA=-55

C to +125

C, post total dose at 25

(3) All inputs switching. DC average current.

DUT

output

Valid low

output

Vref1

CL >50 pF*

249

Tester Equivalent Load Circuit

2.2 V

Valid high

output

Vref2

*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ

HLX6256

HIGH

IMPEDANCE

NCS

NOE

DATA VALID

AVAVR

AVQV

AXQX

SLQV

SLQX

SHQZ

EHQX

EHQV

GLQX

GLQV

GHQZ

ELQZ

ADDRESS

(NWE = high)

DATA OUT

TAVAVR

Address Read Cycle Time

TAVQV

Address Access Time

TAXQX

Address Change to Output Invalid Time

TSLQV

Chip Select Access Time

TSLQX

Chip Select Output Enable Time

TSHQZ

Chip Select Output Disable Time

TEHQV

Chip Enable Access Time (4)

TEHQX

Chip Enable Output Enable Time (4)

TELQZ

Chip Enable Output Disable Time (4)

TGLQV

Output Enable Access Time

TGLQX

Output Enable Output Enable Time

TGHQZ

Output Enable Output Disable Time

READ CYCLE AC TIMING CHARACTERISTICS (1)

Worst Case (3)

Symbol

Parameter

Typical

-55 to 125

Units

(2)

Min Max

(1) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the

Tester AC Timing Characteristics table, capacitive output loading C

>50 pF, or equivalent capacitive output loading C

=5 pF for TSHQZ, TELQZ

TGHQZ. For C

>50 pF, derate access times by 0.02 ns/pF (typical).

(2) Typical operating conditions: VDD=3.3 V, TA=25

C, pre-radiation.

(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, post total dose at 25

(4) Chip Enable (CE) pin not available on 28-lead FP or DIP.

HLX6256

ADDRESS

HIGH

IMPEDANCE

DATA OUT

NWE

DATA IN

DATA VALID

AVAVW

NCS

AVWH

WLWH

AVWL

WLQZ

DVWH

WHQX

WHDX

SLWH

EHWH

WHAX

WHWL

WRITE CYCLE AC TIMING CHARACTERISTICS (1)

Symbol

Parameter

Typical

-55 to 125

Units

(2)

Min Max

Worst Case (3)

TAVAVW

Write Cycle Time

(4)

TWLWH

Write Enable Write Pulse Width

TSLWH

Chip Select to End of Write Time

TDVWH

Data Valid to End of Write Time

TAVWH

Address Valid to End of Write Time

TWHDX

Data Hold Time after End of Write Time

TAVWL

Address Valid Setup to Start of Write Time

TWHAX

Address Valid Hold after End of Write Time

TWLQZ

Write Enable to Output Disable Time

TWHQX

Write Disable to Output Enable Time

TWHWL

Write Disable to Write Enable Pulse Width (5)

TEHWH

Chip Enable to End of Write Time (6)

(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the

Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.

(2) Typical operating conditions: VDD=3.3 V, TA=25

C, pre-radiation.

(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125

C, post total dose at 25

(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) Chip Enable (CE) pin not available on 28-lead FP or DIP.

HLX6256

DYNAMIC ELECTRICAL CHARACTERISTICS

Read Cycle

The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write enable
(NWE) must be high. The output drivers can be controlled
independently by the NOE signal. Consecutive read cycles
can be executed with NCS held continuously low, and with
CE held continuously high, and toggling the addresses.

For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between ad-
dress edge transitions is permissible; however, data outputs
will become valid TAVQV time following the latest occurring
address edge transition. The minimum address activated
read cycle time is TAVAV. When the RAM is operated at the
minimum address activated read cycle time, the data outputs
will remain valid on the RAM I/O until TAXQX time following
the next sequential address transition.

To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS; however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.

To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address
edge transition. Data outputs will enter a high impedance
state TELQZ time following a disabling CE edge transition.

Write Cycle

The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.

The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar, except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Both CE
and NCS fully disable the RAM decode logic and input
buffers for power savings. Only the NWE controlled mode
is shown in the table and diagram on the previous page for
simplicity; however, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.

To write data into the RAM, NWE and NCS must be held low
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tive write operations, write pulses must be separated by the
minimum specified TWHWL/TSHSL/TELEH time. Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.

HLX6256

TESTER AC TIMING CHARACTERISTICS

ing the need to create detailed specifications and offer
benefits of improved quality and cost savings through
standardization.

RELIABILITY

Honeywell understands the Stringent reliability require-
ments for space and defense systems and has extensive
experience in reliability testing on programs of this nature.
This experience is derived from comprehensive testing of
VLSI processes. Reliability attributes of the RICMOS

process were characterized by testing specially designed
irradiated and non-irradiated test structures from which
specific failure mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot carriers,
electromigration and time dependent dielectric breakdown.
This data was then used to make changes to the design
models and process to ensure more reliable products.

In addition, the reliability of the RICMOS

process and

product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is quali-
fied by following a screening and testing flow to meet the
customer's requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.

QUALITY AND RADIATION HARDNESS
ASSURANCE

Honeywell maintains a high level of product integrity through
process control, utilizing statistical process control, a com-
plete "Total Quality Assurance System," a computer data
base process performance tracking system and a radia-
tion-hardness assurance strategy.

The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiating
test structures as well as SRAM product, and then monitor-
ing key parameters which are sensitive to ionizing radia-
tion. Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and con-
tinuing through product qualification and screening.

SCREENING LEVELS

Honeywell offers several levels of device screening to meet
your system needs. "Engineering Devices" are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MIL-
STD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are avail-
able per the applicable Standard Microcircuit Drawing
(SMD). QML devices offer ease of procurement by eliminat-

3 V

0 V

VDD/2

0.4 V

High Z

2.7 V

1.7 V

High Z

Input

Levels*

Output

Sense

Levels

High Z = 2.2V

* Input rise and fall times <1 ns/V

VDD-0.4V

HLX6256

(width)

(pitch)

TOP

VIEW

Capacitor

Pads

[1] BSC Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS

C
D

E2
E3

S
U

X
Y

0.105

0.015

0.017

0.002

0.003 to 0.006
0.720

0.008

0.050

0.005 [1]

0.500

0.007

0.380

0.008

0.060 ref
0.650

0.005 [2]

0.035

0.004

0.295 min [3]
0.026 to 0.045
0.045

0.010

0.130 ref
0.050 ref
0.075 ref
0.010 ref

All dimensions in inches

Lead

Alloy 42 [3]

Ceramic

Body

Kovar

Lid [4]

BOTTOM

VIEW

Index

The 32K x 8 SRAM is offered in a custom 36-lead flat pack
(FP), 28-Lead FP, or standard 28-lead DIP. Each package
is constructed of multilayer ceramic (Al

) and features

internal power and ground planes. The 36-lead FP also
features a non-conductive ceramic tie bar on the lead
frame. The tie bar allows electrical testing of the device,
while preserving the lead integrity during shipping and
handling, up to the point of lead forming and insertion.

PACKAGING

28-LEAD FLAT PACK

(22018131-001)

Ceramic chip capacitors can be mounted to the package by
the user to maximize supply noise decoupling and increase
board packing density. These capacitors attach directly to
the internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire and
package. All NC (no connect) pins must be connected to
either VDD, VSS or an active driver to prevent charge build
up in the radiation environment.

36-LEAD FP PINOUT

VDD
NWE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3

A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

VSS

Top

View

28-LEAD DIP & FP PINOUT

28-LEAD DIP

For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10

VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS

VSS

VDD

A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

VDD

VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

Top

View

HLX6256

VDD = 3.9V, R

10 K

, VIH = VDD, VIL = VSS

Ambient Temperature

125

C, F0

100 KHz Sq Wave

Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.

VDD = 3.6V min., R

10 K

Ambient Temperature

125

36-LEAD FLAT PACK

(22018131-001)

[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS

C
D

E
e
F

G
H

J
L

0.095 ± 0.014
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
0.285 ± 0.015

M
N
O

S
T

X
Y

0.008 ± 0.003
0.050 ± 0.010
0.090 ref
0.015 ref
0.075 ref
0.113 ± 0.010
0.050 ref
0.030 ref
0.080 ref
0.005 ref
0.450 ref
0.400 ref

All dimensions are in inches

[1]

Kovar
Lid [3]

Ceramic

Body

0.004

VDD

Optional

Capacitors

VSS

VDD

VSS

Non-

Conductive

Tie-Bar

(width)

(pitch)

Top

View

22018131-001

F0
F15
F12
F11
F10
F17
F9
F17
F1
F1
F1
F1
F1

VSS

VDD

32K x 8 SRAM

A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VDD

NWE

A13

A8
A9

A11

NOE

A10

NCS

DQ7
DQ6
DQ5
DQ4
DQ3

1 0

1 1

1 2

1 3

1 4

F16

F7
F6
F5
F4
F3
F2
F8

F13
F14

F1
F1
F1

VSS

VDD

32K x 8 SRAM

A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VDD

NWE

A13

A8
A9

A11

NOE

A10

NCS
DQ7
DQ6
DQ5
DQ4
DQ3

VDD

DYNAMIC BURN-IN DIAGRAM*

STATIC BURN-IN DIAGRAM*

*36-lead Flat Pack burn-in diagram has similar connections and is available on request.

HLX6256

Helping You Control Your World

ORDERING INFORMATION (1)

Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

PROCESS

LX=Low Power SOI

SOURCE

H=HONEYWELL

TOTAL DOSE

HARDNESS

R=1x10

rad(SiO

)

F=3x10

rad(SiO

)

H=1x10

rad(SiO

)

N=No Level Guaranteed

SCREEN LEVEL

V=QML Class V

Q=QML Class Q

S=Level S
B=Level B

E=Engineering Device (2)

PACKAGE DESIGNATION

N=28-Lead FP

R=28-Lead DIP

X=36-Lead FP

K=Known Good Die

- = Bare die (No Package)

PART NUMBER

6256

900160
2/96

To learn more about Honeywell Solid State Electronics Center,

visit our web site at http://www.ssec.honeywell.com

(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.

(2) Engineering Device description: Parameters are tested from -55 to 125

C, 24 hr burn-in, no radiation guaranteed.

Contact Factory with other needs.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HLX6256

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HLX6256