_________________________________________________________________________________________________________
Solid State Electronics Center 12001 State Highway 55, Plymouth, MN 55441 (800) 323-8295 http://www.ssec.honeywell.com
MIL-STD-1750A MICROPROCESSOR
HX1750
FEATURES
GENERAL DESCRIPTION
Fabricated on Honeywell's Radiation Hardened
0.65 m L
eff
(0.55 m for 3.3v device) RICMOS
TM
Silicon On Insulator (SOI-IV) process
Choice of supply voltage at 5v or 3.3v with 5v
tolerant inputs.
TTL and CMOS Compatible I/O
3.3 MIPS DAIS Mix Including Floating Point
Maximum Clock Rates 40 Mhz, Fully Static
Separate Address and Data I/O Busses
Two Programmable Timers
Trigger-go Counter
Sixteen Levels of Vectored Interrupts
I/O Maintenance Console Interface
Expanded Addressing to 1Meg with MMU
Total Dose Hardness 1x10
5
rad(Si)
Soft Error Rate < 1x10
-9
Errors/Bit-Day
No Latchup
Low Power
The HX1750 is a true single chip implementation of
the MIL-STD-1750A instruction set architecture,
fabricated on Honeywell's RICMOS
TM
Silicon on
Insulator (SOI-IV) process. It combines a fast 16 bit
microprocessor, a 40 bit floating point processor,
counters, timers and other peripheral interface logic
all on a single chip. Advanced architectural
features, innovative circuit design, and the high
density and performance characteristics of the SOI-
IV process enable device operation up to 40 MHz
over the full military temperature range, even after
exposure to ionizing radiation. The Soft Error Rate
(SER) is less than 1x10
-11
Errors/Bit-Day in the
Adams 90% worst case environment.
The HX1750 offers a wide range of features that
provide for ease of use, versatility and minimum
external components. Simplified memory interface
and adjustable cycle times allows the use of slower,
low cost memory devices.
Most of the options in the MIL-STD-1750A standard
are implemented on the HX1750 chip as listed
below:
Discrete I/O Commands
DMA Commands
Console Interface Commands
Programmed I/O Commands
IOIC Registers
Expanded Memory Addressing
Memory Block Protect
Two Interval Timers
Trigger Go Counter
Start-ROM Support
HX1750
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Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design.
Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein: neither does it
convey any license under its patent rights nor the rights of others. Rev. - 5/03
ORDERING INFORMATION (1)
SOURCE
H=HONEYWELL
H
X
1750
X
S
R
PROCESS
X=SOI
PART NUMBER
PACKAGE DESIGNATION
X= 121-Lead PGA
Y=100-Lead LCC
SCREEN LEVEL
S=Class S (like)
B=Class B (like)
E= Engineering Device (2)
TOTAL DOSE
HARDNESS
R=1x10
N=No Radiation Guaranteed
5 rad (Si)
(1) Orders my be faxed to 763-954-2051.
(2) Engineering Device description: Parameters are tested from -55 C to 125 C, 24 hr burn-
in, No radiation guaranteed. Please contact sales representative with other
requirements.
To learn more about Honeywell Solid State Electronics Center, visit our web site at
http://www.ssec.honeywell.com
or call us at 1-800-323-8295
Several features are incorporated into the
HX1750 to simplify the system interface,
minimize external components, reduce external
memory speed requirements, and ease
software development.
A separate address and data bus eliminates the
need for external PIC chip, address
demultiplexers and latches.
Fast address and data buffers provide signals
early in the cycle allowing use of slower, low
cost memories.
Enhanced Maintenance Console.
Standard memory addressing to 64K
expanded to 1Meg with MMU.
Access Lock and Key implemented.
Simple DMA control implemented
Coprocessor supported in separate address
space.
Variable System clock internal programmable
divider (tie Scale pin high or low) cuts the
internal bus cycle time in half.
Data, Instruction, and I/O access time
independently programmable.
Full synchronous or asynchronous operation
programmable wait states for instructions,
data, and I/O. Asynchronous operation is
slaved to an external RDY signal.
Enhanced set of Built-In-Functions.
Enhanced Configuration Register.
Enhanced Maintenance Console with single
step operation.
The processor executes all mandatory MIL-
STD-1750A instructions including floating
point. Interrupts, fault handling, memory
expansion, and I/O and the optional
instructions related to these operations are
also supported in accordance with MIL-STD-
1750A. All instructions are re-startable after
access faults for true demand paging
operation.
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