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Электронный компонент: GDC21D401B

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GDC21D401B
(Video Decoder)
Version 1.0
Mar, 99
HDS-GDC21D401B-9908 / 10
3
GDC21D401B
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by Hyundai for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Hyundai or others.
These Hyundai products are intended for usage in general electronic equipment (office equipment,
communication equipment, measuring equipment, domestic electrification, etc.).
Please make sure that you consult with us before you use these Hyundai products in equipment which
require high quality and / or reliability, and in equipment which could have major impact to the welfare
of human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these
Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.
Copyright 1999 Hyundai Micro Electronics Co.,Ltd.
All Rights Reserved
4
GDC21D401B
TABLE OF CONTENTS
1. General Description ............................................................................................................5
2. Features ...............................................................................................................................5
3. Pin Description....................................................................................................................6
4. Block Diagram ...................................................................................................................10
5. Functional Description .....................................................................................................11
5.1 Initialization and Decoding Start ...................................................................................11
5.2 Picture Decoding ..........................................................................................................11
5.3 STC (System Time Clock) Generation..........................................................................12
5.4 DTS (Decoding Time Stamp) Synchronization..............................................................12
5.5 Error Concealment .......................................................................................................12
5.6 User Data Read............................................................................................................12
5.7 Bitstream Buffer Over/Underflow..................................................................................13
5.8 VLD (Variable Length Decoder) ....................................................................................13
5.9 Inverse Quantization ....................................................................................................13
5.10 IDCT (Inverse Discrete Cosine Transform) .................................................................13
5.11 MC(Motion Compensation) .........................................................................................13
5.12 Transport Interface .....................................................................................................14
5.13 Host Interface .............................................................................................................15
5.14 Video Data Output Format..........................................................................................20
5.15 Video Data Output Timing ..........................................................................................21
5.16 SDRAM Interface .......................................................................................................22
6. Electrical Specification .....................................................................................................24
6.1 Absolute Maximum Rating............................................................................................24
6.2 Recommended Operating Range .................................................................................24
6.3 DC Characteristics (VDD = 3.3 V10%, TA = 0 ~ 70
) ................................................24
6.4 AC Characteristics (VDD = 3.3 V10%, TA = 0 ~ 70
) ................................................25
7. Package Mechanical Data .................................................................................................26
7.1 Package Pin Out ..........................................................................................................26
7.2 Physical Dimension ......................................................................................................29
5
GDC21D401B
1. General Description
The Video Decoder(VD) decodes video
elementary stream of MPEG-2(ISO/ICE
13818-2)MP@HL. It supports the ATSC
digital TV video standard, and can be used for
the video part of the ATSC digital TV with the
Transport Decoder and the VDP(Video
Display Processor). Picture decoding timing
can be controlled internally for A/V lip
synchronization, and externally for Video
Trick Mode by host microprocessor via I
2
C bus.
The Video Decoder can extract video user data
including caption from video elementary
stream, and host microprocessor can read the
video user data from the Video Decoder(VD)
via I
2
C. It uses four 16x1M SDRAMs and can
support up to 81 MHz memory clock speed.
2. Features
Supports MPEG-2 (ISO/ICE 13818-2)
MP@HL
Supports all video input formats of ATSC
digital TV standard
Supports picture decoding capability up to
1920x1088 30 Frame/Sec
Supports all kinds of motion compensation
methods of MPEG-2
Supports MPEG-2 error code, syntax error
detection, and slice-based error concealment
Supports DTS synchronization
Supports VBV delay mode and low delay
mode decoding
Supports film mode decoding (3:2 Pull
down)
Supports high level commands for trick
mode
Supports 8(w)x64(d) internal user data FIFO
Outputs: macroblock format
4-pel parallel output
54 MHz synchronous I/F
Data window (pdwin, sclk, and mbclk)
Picture information (Picture structure, Field
parity, and DCT type)
External memory for VBV buffer , DTS
FIFO and 2-frame memory:
64-bit Data Bus
81 MHz Synchronous Interface
64-Mbyte
Four 16x1M SDRAMs
Host processor interface: I
2
C bus interface
Two interrupt signals
Supports 23 programmable internal
registers
GDC21D401B
Video Decoder
6
GDC21D401B
3. Pin Description
6 0
1 8 0
2 4 0
1
H M E
G D C 2 1 D 4 0 1 B
Y Y W W A
V S S
S C A N T E S T O N
V D D
I D C T T E S T O N
M E M T E S T O N
C L K _ 2 7 M
V S S
\ R E S E T
T S W
\ V I D E N
V S T C W
V S S
V I D _ S T R B
V I D _ D A T A [ 0 ]
V I D _ D A T A [ 1 ]
V I D _ D A T A [ 2 ]
V D D
V I D _ D A T A [ 3 ]
V S S
V I D _ D A T A [ 4 ]
V I D _ D A T A [ 5 ]
V D D
V I D _ D A T A [ 6 ]
V S S
V I D _ D A T A [ 7 ]
S C L
V S S
S D A
\ V I D _ R E Q
\ U B U F F _ F U L L
\ I N T _ V
V D D
S D R A M _ D A T A [ 0 ]
S D R A M _ D A T A [ 1 ]
V S S
S D R A M _ D A T A [ 2 ]
V D D
S D R A M _ D A T A [ 3 ]
S D R A M _ D A T A [ 4 ]
S D R A M _ D A T A [ 5 ]
V D D
S D R A M _ D A T A [ 6 ]
S D R A M _ D A T A [ 7 ]
V D D
S D R A M _ D A T A [ 8 ]
V S S
S D R A M _ D A T A [ 9 ]
S D R A M _ D A T A [ 1 0 ]
V D D
S D R A M _ D A T A [ 1 1 ]
S D R A M _ D A T A [ 1 2 ]
V S S
S D R A M _ D A T A [ 1 3 ]
S D R A M _ D A T A [ 1 4 ]
V D D
S D R A M _ D A T A [ 1 5 ]
S D R A M _ D A T A [ 1 6 ]
V S S
S D R A M _ D A T A [ 1 7 ]
S D R A M _ D A T A [ 1 8 ]
SDRAM_
DATA[38]
VDD
SDRAM_
DATA[37]
SDRAM_
DATA[36]
SDRAM_
DATA[35]
VSS
SDRAM_
DATA[34]
SDRAM_
DATA[33]
SDRAM_
DATA[32]
VDD
VDD
CSN
RASN
CASN
WEN
VSS
BA0
SDRAM_
ADDR[10]
SDRAM_
ADDR[9]
SDRAM_
ADDR[8]
VDD
SDRAM_
ADDR[7]
SDRAM_
ADDR[0]
VSS
VSS
VSS
MCLK
VDD
SDRAM_
ADDR[6]
SDRAM_
ADDR[1]
VDD
SDRAM_
ADDR[5]
VDD
SDRAM_
ADDR[2]
SDRAM_
ADDR[4]
VSS
SDRAM_
ADDR[3]
VSS
SDRAM_
DATA[31]
SDRAM_
DATA[30]
VDD
SDRAM_
DATA[29]
SDRAM_
DATA[28]
VSS
SDRAM_
DATA[27]
SDRAM_
DATA[26]
VDD
SDRAM_
DATA[25]
SDRAM_
DATA[24]
VDD
SDRAM_
DATA[23]
VSS
SDRAM_
DATA[22]
VDD
SDRAM_
DATA[21]
VSS
SDRAM_
DATA[20]
VDD
SDRAM_
DATA[19]
VSS
V S S
P S T R [ 1 ]
P S T R [ 0 ]
P D W I N
V S S
D _ I N F O _ W I N
D I S _ I N F O
V D D
V D D
\ F F P N
V S S
M B F I
M B C L K
V D D
S C L K
V D C L K
V S S
S D R A M _ D A T A [ 6 3 ]
S D R A M _ D A T A [ 6 2 ]
S D R A M _ D A T A [ 6 1 ]
V D D
V D D
S D R A M _ D A T A [ 6 0 ]
S D R A M _ D A T A [ 5 9 ]
V S S
V S S
S D R A M _ D A T A [ 5 8 ]
V D D
S D R A M _ D A T A [ 5 7 ]
V S S
S D R A M _ D A T A [ 5 6 ]
V D D
S D R A M _ D A T A [ 5 5 ]
S D R A M _ D A T A [ 5 4 ]
V S S
S D R A M _ D A T A [ 5 3 ]
S D R A M _ D A T A [ 5 2 ]
V D D
S D R A M _ D A T A [ 5 1 ]
S D R A M _ D A T A [ 5 0 ]
V S S
S D R A M _ D A T A [ 4 9 ]
S D R A M _ D A T A [ 4 8 ]
V D D
S D R A M _ D A T A [ 4 7 ]
V D D
S D R A M _ D A T A [ 4 6 ]
S D R A M _ D A T A [ 4 5 ]
V S S
V S S
S D R A M _ D A T A [ 4 4 ]
V D D
S D R A M _ D A T A [ 4 3 ]
V D D
S D R A M _ D A T A [ 4 2 ]
S D R A M _ D A T A [ 4 1 ]
V S S
S D R A M _ D A T A [ 4 0 ]
V S S
S D R A M _ D A T A [ 3 9 ]
P_SHARE_
IN[10]
P_SHARE_
IN[9]
P_SHARE_
IN[8]
MCLK_OUT
TEST_ OUT[2]
FP_FD
MCLK_IN
DEC_ERROR
VSS
P_WAIT
PIC_DIS_SYNC
VDD
VDD
PDATA[31]
PDATA[30]
PDATA[29]
PDATA[28]
VSS
VSS
PDATA[27]
PDATA[26]
PDATA[25]
PDATA[24]
VDD
PDATA[23]
PDATA[22]
PDATA[21]
PDATA[20]
VSS
PDATA[19]
PDATA[18]
VDD
PDATA[17]
PDATA[16]
PDATA[15]
VDD
PDATA[14]
PDATA[13]
PDATA[12]
VSS
PDATA[11]
VSS
PDATA[10]
VDD
PDATA[9]
PDATA[8]
VDD
PDATA[7]
PDATA[6]
PDATA[5]
PDATA[4]
VSS
VSS
PDATA[3]
VDD
VDD
PDATA[2]
PDATA[1]
PDATA[0]
VSS
1 7 5
1 7 0
1 6 5
1 6 0
1 5 5
1 5 0
1 4 5
1 4 0
1 3 5
1 3 0
1 2 5
5
1 0
1 5
2 0
2 5
3 0
3 5
4 0
4 5
5 0
5 5
65
70
75
80
85
90
95
100
105
110
115
120
190
185
195
200
205
210
215
220
225
230
235
Figure 1. Pin Description