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GMS81C5108

JUNE 2001 Ver 1.0

Table of Contents

1. OVERVIEW ...........................................1

Description .........................................................1
Features .............................................................1
Development Tools ............................................2
Ordering Information

2. BLOCK DIAGRAM ................................3

3. PIN ASSIGNMENT ...............................4

4. PACKAGE DIAGRAM ...........................5

5. PIN FUNCTION .....................................6

6. PORT STRUCTURES ...........................8

7. ELECTRICAL CHARACTERISTICS ...11

Absolute Maximum Ratings .............................11
Recommended Operating Conditions ..............11
DC Electrical Characteristics ...........................12
LCD Characteristics .........................................13
A/D Converter Characteristics .........................13
AC Characteristics ...........................................14
Serial I/O Characteristics .................................15
Typical Characteristics ..................................... 16

8. MEMORY ORGANIZATION ................18

Registers ..........................................................18
Program Memory .............................................21
Data Memory ................................................... 24
Addressing Mode ............................................. 27

9. I/O PORTS ..........................................31

Registers for Port .............................................31
I/O Ports Configuration ....................................32

10. CLOCK GENERATOR ......................34

Operation Mode ...............................................36
Operation Mode Switching ...............................37
POWER SAVING OPERATION .......................39

11. BASIC INTERVAL TIMER .................43

12. Timer / Counter .................................45

8-Bit Timer/Counter Mode ................................48
16 Bit Timer/Counter Mode ..............................50

8-Bit Capture Mode ......................................... 50
16-bit Capture Mode ....................................... 53
8-Bit (16-Bit) Compare OutPut Mode .............. 53
PWM Mode ..................................................... 53

13. Watch Timer/Watch Dog Timer......... 56

Watch Timer .................................................... 56
Watch Dog Timer ............................................ 57

14. Analog To Digital Converter ..............58

15. Buzzer Output Function ....................60

16. Serial Communication Interface ........62

Data Transmit/Receive Timing........................ 63
The method of Serial I/O ................................. 64

17. INTERRUPTS ...................................65

Interrupt Sequence .......................................... 66
BRK Interrupt .................................................. 68
Multi Interrupt .................................................. 68
External Interrupt ............................................. 69

18. KEY SCAN ........................................70

19. LCD DRIVER .................................... 71

Configuration of LCD driver ............................. 71
Control of LCD Driver Circuit ........................... 72
LCD Display Memory ...................................... 73
Control Method of LCD Driver ......................... 74

20. Remocon Carrier Generator ............. 76

Remocon Signal Output Control ..................... 76
Carrier Frequency ........................................... 77

21. OSCILLATOR CIRCUIT ....................80

22. RESET ..............................................81

External Reset Input ........................................ 81
Watchdog Timer Reset ................................... 81

23. SUPPLY VOLTAGE DETECTION ....82

24. DEVEMOPMENT TOOLS .................83

OTP Programming .......................................... 83
Emulator S/W Setting ...................................... 84

A. CONTROL REGISTER LIST ................. i

B. INSTRUCTION .................................... iii

Terminology List................................................ iii

Instruction Map ..................................................iv
Instruction Set ....................................................v

C. MASK ORDER SHEET ....................... xi

GMS81C5108

JUNE 2001 Ver 1.0

GMS81C5108

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH LCD CONTROLLER/DRIVER AND

INFRARED REMOTE CONTROL TRANSMITTERS

1. OVERVIEW

1.1 Description

The GMS81C5108 is an advanced CMOS 8-bit microcontroller with 8K bytes of ROM. The device is one of GMS800 fam-
ily. The Hynix GMS81C5108 is a powerful microcontroller which provides a high flexibility and cost effective solution to
many LCD applications. The GMS81C5108 provides the following standard features: 8K bytes of ROM, 192 bytes of RAM,
37 Nibbles of Display RAM, 8/16-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the GMS81C5108
supports power saving modes to reduce power consumption.
This document is only explained for the base of GMS81C5108, the eliminated functions are same as below.

1.2 Features

· 8K Bytes of On-chip Program Memory

· 192 Bytes of On-chip Data RAM

· 37 Nibbles of Display RAM

· Instruction Cycle Time:

- 1us at 4MHz (2 cycle NOP instruction)

· 24 Programmable I/O pins

· 2V to 4V Operating Range

· Dual Clock Operation

- main : 400kHz ~ 4.2MHz
- sub. : 32.768kHz

· One 8-bit Basic Interval Timer/Counter

· Key Scan Interrupt

· Two 8-bit Timer/ Counter

(It can be used one 16-bit Timer/Counter)

· Watch Timer (2Hz, 4Hz, 16Hz, 1/64Hz)

· 8-bit Serial I/O (SIO)

· One 10-bit High Speed PWM Output

· Carrier Generator for Remote Controller

· 11 Interrupt sources

- 3 External interrupts (INT0 ~ 2)
- 8 Internal interrupts (BIT, Timer

2, WT,

A/DC, SIO, REM, Keyscan)

· 6-bit Buzzer Driving port

- 500Hz ~ 250kHz (@4MHz)

· 4-channel 8-bit On-chip A/D Converter

· Power Saving Mode

- STOP, SLEEP, Sub Active mode

· LCD display/controller (LCDC)

- Static Mode (37Seg

1Com, 1/3 Bias)

- 1/2 Duty Mode (36Seg

2Com, 1/3 Bias)

- 1/3 Duty Mode (35Seg

3Com, 1/3 Bias)

- 1/4 Duty Mode (34Seg

4Com, 1/3 Bias)

· LCD Display Voltage Booster

· Supply Voltage Detector(SVD)

- 2 level detector (2.2V, 1.7V)

Device name

ROM Size

OTP Size

RAM Size

I/O

Package

GMS81C5108

8K bytes

192 bytes

80QFP

GMS87C5108

8K bytes

192bytes

80QFP

GMS81C5108

JUNE 2001 Ver 1.0

1.3 Development Tools

Note: There are several setting switches in the Emulator.
User should read carefully and do setting properly before
developing the program refer to "24.2 Emulator S/W Set-
ting" on page 84. Otherwise, the Emulator may not work
properly.

The GMS81C5108 is supported by a full-featured macro assem-
bler, an in-circuit emulator CHOICE-Dr.

and OTP program-

mers. There are two different type programmers such as single
type and gang type. For mode detail, refer to OTP Programming
chapter. Macro assembler operates under the MS-Windows 95/

Please contact sales part of Hynix Semiconductor.

1.4 Ordering Information

Software

- MS- Window base assembler
- Linker / Editor / Debugger

Hardware
(Emulator)

- CHOICE-Dr.
- CHOICE-Dr. EVA 81C51 B/D

OTP Writer

- CHOICE - SIGMA (Single writer)
- CHOICE - GANG4 (Gang writer)

Device name

ROM Size (bytes)

RAM size

Package

Mask ROM version

GMS81C5108

8K bytes

192 bytes

80QFP

OTP ROM version

GMS87C5108

8K bytes OTP

192 bytes

80QFP

GMS81C5108

JUNE 2001 Ver 1.0

2. BLOCK DIAGRAM

ALU

LCD Controller/Driver (LCDC)

Accumulator

Stack Pointer

Interrupt Controller

Data

Memory

LCD

Memory

Display

Program

Memory

Data Table

8-bit B asic

Interval Tim er

High Speed

Buzzer

Driver

PSW

System controller

Timing generator

System

Clock Controller

Clock

Generator

High freq.

Low freq.

RESET

OUT

Segment Drive Output

SEG0 ~ SEG33

Common Drive Output

COM0

R00 / INT0
R01 / INT1
R02 / INT2
R03 / EC0
R04 / BUZ
R05 / SCK
R06 / SO
R07 / SI

R10 / KS0
R11 / KS1
R12 / KS2
R13 / KS3
R14 / KS4
R15 / KS5
R16 / KS6
R17 / KS7

R30

Power
Supply

VCL0
VCL1
VCL2

COM1/SEG36
COM2/SEG35
COM3/SEG34

LCD Display

Voltage Booster

CAPH
CAPL
VLCDC

Power

Supply

Circuit

VREG

R20 / AN0

R31 / PWM
R32
R33

R21 / AN1
R22 / AN2
R23 / AN3

8-bit A /D

C onverter

PWM

8/16-bit

T im er/C ounter

SIO

Watch/Watch Dog

Timer

WDTOUT

Remocon

(REM)

REMOUT

GMS81C5108

JUNE 2001 Ver 1.0

3. PIN ASSIGNMENT

R23 / AN3

R22 / AN2

R21 / AN1

R20 / AN0

SEG0

VSS

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

RESET

VREG

WDTOUT

OUT

VCL0

VLCDC

VCL1

VCL2

CAPH

CAPL

COM0

SEG36 / COM1

SEG35 / COM2

SEG34 / COM3

SEG33

OUT

MOUT

R07 /

R06 /

R05 /

SCK

R04 /

BUZ

R03 /

EC0

R02 /

R01 /

R33

R32

R31 /

R30

R17 /

R16 /

R15 /

R14 /

R13 /

R12 /

R11 /

R10 /

R00 /

GMS81C5108

JUNE 2001 Ver 1.0

5. PIN FUNCTION

: Supply voltage.

: Circuit ground.

: Supply voltage to the ladder resistor of ADC cir-

cuit. To enhance the resolution of analog to digital convert-
er, use independent power source as well as possible, other
than digital power source.

: ADC circuit ground

RESET: Reset the MCU.

WDTOUT: Output for detection of a program malfunc-
tion. If the user wants to use this pin, connect it to the RE-
SET pin.

REMOUT: Signal output of an infrared remote controller.

: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

OUT

: Output from the inverting oscillator amplifier.

: Input to the internal sub system clock operating cir-

cuit.

OUT

: Output from the inverting subsystem oscillator

amplifier.

SEG0~SEG36: Segment signal output pins for the LCD
display. See "19. LCD DRIVER" on page 71 for details.

COM0~COM3: Common signal output pins for the LCD
display. See "19. LCD DRIVER" on page 71 for details.

SEG34~SEG36 and COM1~COM3 are selected by LCDD
of the LCR register.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

Also, pull-up resistors and open-

drain outputs can be assigned by software.

In addition, R0 serves the functions of the various follow-
ing special features.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs

or schmitt trigger inputs. Also, pull-

up resistors and open-drain outputs can be assigned by software.

In addition, R1 serves the functions of the various follow-
ing special features.

R20~R23: R2 is a 4-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

Also, pull-up resistors and open-

drain outputs can be assigned by software.

In addition, R2 serves the functions of the various follow-

ing special features

R30~R33: R3 is a 4-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

Also, pull-up resistors and open-

drain outputs can be assigned by software.

In addition, R3 serves the functions of the various follow-

ing special features

VCL0~VCL2: Power supply pins for the LCD driver. The
voltage on each pin is VCL2

VCL1

VCL0. See "19.

LCD DRIVER" on page 71 for details.

VLCDC: LCD drive voltage booster reference.

CAPH, CAPL: LCD drive voltage booster capacitor.

VREG: Output of the voltage regular for the sub clock os-
cillation circuit. Connect external 0.1uF capacitor to this
pin when using the sub system clock.

Port pin

Alternate function

R00
R01
R02
R03
R04
R05
R06
R07

INT0 (External interrupt 0)
INT1 (External interrupt 1)
INT2 (External interrupt 2)
Event counter input
Buzzer Output
SCK (SPI CLK Input/Output)
SO (SPI Serial Data Output)
SI (SPI Serial Data Input)

Port pin

Alternate function

R10
R11
R12
R13
R14
R15
R16
R17

KS0 (Key scan input 0)
KS1 (Key scan input 1)
KS2 (Key scan input 2)
KS3 (Key scan input 3)
KS4 (Key scan input 4)
KS5 (Key scan input 5)
KS6 (Key scan input 6)
KS7 (Key scan input 7)

Port pin

Alternate function

R20
R21
R22
R23

AN0 (Analog Input Port0)
AN1 (Analog Input Port1)
AN2 (Analog Input Port2)
AN3 (Analog Input Port3)

Port pin

Alternate function

R31

PWM (PWM Output)

GMS81C5108

JUNE 2001 Ver 1.0

PIN NAME

Pin No.

Primary Function

Secondary Function

State @ Reset

State @ STOP

I/O

Description

I/O

Description

Supply Voltage

Circuit Ground

Supply Voltage for

ADC

Ground for ADC

RESET

Reset (low active)

`L' input

`H' input

WDTOUT

Watch dog output

Floating (To be

connect Pull-up)

State of before

STOP

REMOUT

Remocon output

`L' output

IN,

OUT

63, 64

I,O

Main clock oscillator

Oscillation

`L', `L'

IN,

OUT

68, 69

I,O

Sub clock oscillator

Oscillation

REG

Sub clock voltage

VCL0~VCL2

70,72,73

LCD drive voltage

Internal VCL0

Connected

State of before

STOP

VLCDC

LCD drive voltage

booster reference

CAPH,CAPL

74,75

LCD drive voltage

booster capacitor

Internal VCL0

Connected

State of before

STOP

SEG0 ~ SEG33 34, 32~1

LCD segment output

Segment output

COM0

LCD common output

Common output

SEG34/COM3
SEG35/COM2
SEG36/COM1

79~77

LCD common output.

LCD segment

output

Common output

State of before

STOP

R00/INT0

I/O

General I/O port

Interrupt Input

Input port

R01/INT1

I/O

Interrupt Input

R02/INT2

I/O

Interrupt Input

R03/EC0

I/O

Event counter input

R04/BUZ

I/O

Buzzer output

R05/SCK

I/O

Serial clock I/O

R06/SO

I/O

Serial Data Output

R07/SI

I/O

Serial Data Input

R10 ~ R17/
KS0 ~ KS7

42~49

I/O

Key wake-up input

R20 ~ R23/
AN0 ~ AN3

36~39

I/O

A/D converter

analog input

R30,R32,R33

50,52,53

I/O

R31/PWM

I/O

PWM output

Table 5-1 Port Function Description

GMS81C5108

JUNE 2001 Ver 1.0

6. PORT STRUCTURES

R00~R03/INT0~INT2, R03/EC0, R07/SI

R04/BUZ, R06/SO

R05/SCK

R10~R17/KS0~KS7

R20~R23/AN0~AN3

Data Reg.

Dir. Reg.

Noise

Canceller

IN T0 ~ IN T2

P u ll up

R e g.

M U X

Pull-up Tr.

EC0,SI

Open Drain

Reg.

PMR<0:3,7>

Data Reg.

Dir. Reg.

Pull up

Reg.

M U X

Pull-up Tr.

Open Drain

Reg.

BUZ,SO

t
a

Data Reg.

Dir. Reg.

Pull up

Reg.

M U X

Pull-up Tr.

Open Drain

Reg.

SCK(OUT)

Noise

Canceller

SCK(IN)

SCK(IN)_EN

Data Reg.

Dir. Reg.

P ull up

R eg .

M U X

Pull-up Tr.

Open Drain

Reg.

Key Scan

Key Scan
Enable

KS0 ~ KS7

Noise

Canceller

KSMR<0:7>

Data Reg.

Dir. Reg.

P u ll up

R e g.

M U X

Pull-up Tr.

Open Drain

Reg.

A/D converter

AN0 ~ AN3

A/D Enable

channel select

GMS81C5108

JUNE 2001 Ver 1.0

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage ........................................... -0.3 to +7.0 V

Storage Temperature ................................-40 to +125

Voltage on any pin with respect to Ground (V

)

............................................................... -0.3 to V

+0.3

Maximum current sunk by (I

per I/O Pin) ........20 mA

Maximum output current sourced by (I

per I/O Pin)

...............................................................................15 mA

Maximum current (

) ....................................100 mA

Maximum current (

)...................................... 60 mA

Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.

7.2 Recommended Operating Conditions

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

Supply Voltage

MAIN

=4MHz

SUB

=32.768kHz

2.0

4.0

Main Operating Frequency

MAIN

=2~4V

0.4

4.2

MHz

Sub Operating Frequency

SUB

=2~4V

32.768

kHz

Operating Temperature

OPR

-20

GMS81C5108

JUNE 2001 Ver 1.0

7.3 DC Electrical Characteristics

(TA=-20~70

C, V

=AV

=2~4V, V

=AV

=0V)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

Input High Voltage

IH1

R0~R3

0.7V

IH2

RESET, X

, INT0~INT2, EC0, SI, SCK

0.8V

IH3

0.8VREG

VREG

Input Low Voltage

IL1

R0~R3

0.3 V

IL2

RESET, X

, INT0~INT2, EC0, SI, SCK

0.2V

IL3

0.2VREG

Output High Voltage

OH1

R0~R3, I

OH1

=-0.7mA

-0.3

OH2

OUT

, I

OH2

=-50

-0.5

OH3

OUT

, I

OH3

=-5

VREG-0.3

Output Low Voltage

OL1

R0~R3, WDTOUT, I

OL1

=1mA

0.4

OL2

OUT

, I

OL2

=50

0.5

OL3

OUT

, I

OL3

0.5

Input High
Leakage Current

R0~R3, V

Input Low
Leakage Current

R0~R3, V

=0V

-1

Output High
Leakage Current

REMOUT, V

=3V, V

= V

-1.0V

-30

-5

Output Low
Leakage Current

REMOUT, V

=3V, V

= 1.0V

0.5

Pull-up Resister

R0~R3, V

=3V

100

200

RESET, V

=3V

(GMS81C5108 Mask Option)

120

Feed Back Resister

Main OSC Feedback Resister V

=3V

0.5

1.5

Sub OSC Feedback Resister V

=3V

RC Oscillator
Frequency

R=30k

, V

=3V

MHz

VREG Voltage

VREG

VREG=0.2uF

2.0

2.2

2.4

Supply Current

DD1

Main Active Mode
V

=4V

10%, X

=4MHz, SX

2.7

4.0

DD2

Main Sleep Mode
V

=4V

10%, X

=4MHz, SX

0.47

1.2

DD3

Stop Mode
V

D D

=4V

10% , X

=0, SX

2.0

DD4

Sub Active mode

=3V

10%, X

=0, S

XIN

=32.768kH z

35(70)

80(150)

DD5

Sub Sleep mode
V

=4V

10%, X

=0, S

XIN

=32.768kH z

6.0

1. I

DD4 is tested by only nop operation. The value of ( ) is tested at OTP.

GMS81C5108

JUNE 2001 Ver 1.0

7.4 LCD Characteristics

(TA=-20~70

C, V

=AV

=2~4V, V

=AV

=0V)

7.5 A/D Converter Characteristics

(TA=25

C, V

=3V, AV

=3.072V, V

=AV

=0V)

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

VLCDC Output Voltage

VLCDC

=3V, TA=25

R1=1M

300k

0.7

0.9

1.1

LCD Reference
Output Voltage

VCL0

External Variable Resistance
(0 to 1M

)

0.9

2.0

Double Output Voltage

VCL1

C1~C4=0.47uF

1.9VCL0

2.0VCL0

Triple Output Voltage

VCL2

C1~C4=0.47uF

2.85VCL0

3.0VCL0

LCD Common
Output Current

COM

Output Voltage Deviation=0.2V

LCD Segment
Output Current

SEG

Output Voltage Deviation=0.2V

Parameter

Symbol

Condition

Specifications

Unit

Min.

Typ.

Max.

Analog Power Supply Input Voltage Range

Analog Input Voltage Range

-0.3

+0.3

Current Following Between AV

and AV

IAV

200

Overall Accuracy

CAIN

1.0

2.0

LSB

Non Linearity Error

NNLE

1.0

2.0

Differential Non Linearity Error

NDNLE

1.0

2.0

Zero Offset Error

NZOE

0.5

1.5

Full Scale Error

NFSE

0.25

0.5

Gain Error

NGE

1.0

1.5

Conversion Time

TCONV

MAIN

=4MHz

GMS81C5108

JUNE 2001 Ver 1.0

7.6 AC Characteristics

(TA=25

C, V

=4V, AV

=4V, V

=AV

=0V)

Figure 7-1 AC Timing Chart

Parameter

Symbol

Pins

Specifications

Unit

Min.

Typ.

Max.

Main Operating Frequency

MCP

0.455

4.19

MHz

Sub Operating Frequency

SCP

32.768

kHz

System Clock Frequency

SYS

0.477

4.395

Main Oscillation
Stabilization Time (4MHz)

MST

, X

OUT

Main Oscillation
Stabilization Time (910kHz)

Main Oscillation
Stabilization Time (455kHz)

100

Sub Oscillation
Stabilization Time

SST

, SX

OUT

External Clock
"H" or "L" Pulse Width

MCPW

SCPW

Interrupt Pulse Width

INT0, INT1, INT2

SYS

RESET Input Pulse "L" Width

RST

RESET

SYS

Event Counter Input
"H" or "L" Pulse Width

ECW

EC0

SYS

1.SCMR=XXXX000X that is f

MAIN

0.2V

0.8V

0.2V

RESET

0.2V

0.8V

EC0

RST

ECW

1/f

MCP

MCPW

0.2V

0.8V

1/f

SCP

SCPW

SYS

GMS81C5108

JUNE 2001 Ver 1.0

7.8 Typical Characteristics

These graphs and tables are for design guidance only and
are not tested or guaranteed.

In some graphs or tables, the datas presented are out-
side specified operating range (e.g. outside specified
V

range). This is for information only and devices

are guaranteed to operate properly only within the
specified range.

The data is a statistical summary of data collected on units
from different lots over a period of time. "Typical" repre-
sents the mean of the distribution while "max" or "min"
represents (mean + 3

) and (mean

) respectively

where

is standard deviation

, V

=4.2V

(mA)

1.0

3.0

2.0

(V)

, V

=4.2V

-8

-6

-4

-2

(mA)

1.0

2.0

(V)

R0,R1,R2,R3 pin

-
-
-
-

200

100

)

-25

(

=4.0V

-
-
-
-

100

)

-25

(

RESET pin

MAIN

=4MHz

IH1

(V)

IH1

2.5

3.5

(V)

Ta=25

R0~R3 pin

-10

-12

-14

3.0

MAIN

=4MHz

IH2

(V)

IH2

2.5

3.5

(V)

Ta=25

RESET,X

,INT0~INT2,EC0.SI.SCK

-16

4.0

-20

4.0

-20

=4.0V

MAIN

=4MHz

IL2

(V)

IL1

2.5

3.5

(V)

Ta=25

RESET,X

,INT0~INT2,EC0.SI.SCK

MAIN

=4MHz

IL1

(V)

IL1

2.5

3.5

(V)

Ta=25

R0~R3 pin

GMS81C5108

JUNE 2001 Ver 1.0

SLEEP

(

DD5

)

(

2.5

3.5

(V)

Sleep Mode (Sub opr.)

Ta= -20~70

(Main-clock)

Ta=25

MAIN

(MHz)

MAIN

2.5

3.5

(V)

Ta=25

R = 47k

DD1

(mA)

2.5

3.5

(V)

Normal Mode (Main opr.)

(MHz)

MAIN

2.5

3.5

4.5

(V)

Operating Area

STOP

(

DD3

)

(

2.5

3.5

(V)

Stop Mode

DD4

100

(

2.5

3.5

(V)

Normal Mode (Sub opr.)

SLEEP

(

DD2

)

400

300

200

100

(

2.5

3.5

(V)

Sleep Mode (Main opr.)

MAIN

=4MHz

SXIN

=32kHz

Ta=25

MAIN

=0Hz

R = 68k

S X IN

= 3 2 kH z

Ta=25

MAIN

=4MHz

R = 100k

R = 20k

GMS81C5108

JUNE 2001 Ver 1.0

8. MEMORY ORGANIZATION

The GMS81C5108 has separate address spaces for Pro-
gram memory, Data Memory and Display memory. Pro-
gram memory can only be read, not written to. It can be up

to 8K bytes of Program memory. Data memory can be read
and written to up to 192 bytes including the stack area. Dis-
play memory has prepared 37 bytes for LCD.

8.1 Registers

This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

Figure 8-1 Configuration of Registers

Accumulator: The Accumulator is the 8-bit general pur-
pose register, used for data operation such as transfer, tem-
porary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y
Register as shown below.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the spec-
ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have in-
crement, decrement, comparison and data transfer func-
tions, and they can be used as simple accumulators.

Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).

Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.

The stack can be located at any position within 00

to BF

of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
with which the use of the stack starts) by using the initial-
ization routine. Normally, the initial value of "BF

used.

Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset rou-
tine address (PC

:0FF

, PC

:0FE

Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

ACCUMULATOR

X REGISTER

Y REGISTER

STACK POINTER

PROGRAM COUNTER

PROGRAM STATUS
WORD

PCL

PCH

PSW

Two 8-bit Registers can be used as a "YA" 16-bit Register

Caution:

The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.

Example: To initialize the SP

LDX

#0BFH

TXSP

; SP

Stack Address (00

~ BF

)

Hardware fixed

GMS81C5108

JUNE 2001 Ver 1.0

[Zero flag Z]

This flag is set when the result of an arithmetic operation

or data transfer is "0" and is cleared by any other result.

Figure 8-3 PSW (Program Status Word) Register

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00

to 0FF

when this flag is "0". If it is set to "1",

addressing area is assigned by RPR register (address
0F3

). It is set by SETG instruction and cleared by CLRG.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds

127 (7F

) or

128 (80

). The CLRV instruction

clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.

NEGATIVE FLAG

MSB

LSB

RESET VALUE : 00

PSW

OVERFLOW FLAG

BRK FLAG

CARRY FLAG RECEIVES

ZERO FLAG

INTERRUPT ENABLE FLAG

CARRY OUT

HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

SELECT DIRECT PAGE

when g=1, page is addressed by RPR

GMS81C5108

JUNE 2001 Ver 1.0

8.2 Program Memory

A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 8K bytes program memory
space only physically implemented. Accessing a location
above FFFF

will cause a wrap-around to 0000

Figure 8-5 shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFF

as shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fixed loca-
tion in Program Memory. Program Memory area contains
the user program.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.

Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2

for

TCALL14, etc., as shown in Figure 8-7.

Example: Usage of TCALL

The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFA

. The interrupt service locations spaces 2-byte

interval: 0FFF8

and 0FFF9

for External Interrupt 1,

0FFFA

and 0FFFB

for External Interrupt 0, etc.

Any area from 0FF00

to 0FFFF

, if it is not going to be

used, its service location is available as general purpose
Program Memory.

Figure 8-6 Interrupt Vector Area

PROGRAM

MEMORY

TCALL

AREA

INTERRUPT

VECTOR AREA

E000

FEFF

FF00

FFC0

FFDF

FFE0

FFFF

PCALL

AREA

LDA

#5
TCALL 0FH

;1BYTE INSTRUCTION

;INSTEAD OF 2 BYTES

;NORMAL CALL

;
;TABLE CALL ROUTINE
;
FUNC_A:

LDA

LRG0

RET

;
FUNC_B:

LDA

LRG1

RET

;
;TABLE CALL ADD. AREA
;

ORG

0FFC0H

;TCALL ADDRESS AREA

FUNC_A

FUNC_B

0FFE0

Address

Vector Area Memory

Serial I/O Interrupt Vector Area

AD Converter Interrupt Vector Area

Remocon Interrupt Vector Area

Timer/Counter 1 Interrupt Vector Area

Timer/Counter 0 Interrupt Vector Area

External Interrupt 1 Vector Area

Basic Interval Timer Interrupt Vector Area

Key Scan Interrupt Vector Area

RESET Vector Area

External Interrupt 0 Vector Area

External Interrupt 2 Vector Area

Watch Timer Interrupt Vector Area

"-" means reserved area.

NOTE:

GMS81C5108

JUNE 2001 Ver 1.0

Example: The usage software example of Vector address and the initialize part.

ORG

0FFE0H

NOT_USED

WT_INT

; Watch Timer

SIO

; Serial I/O

AD_Con

; AD converter

Carrier_INT

; Carrier

INT2

; Int.2

TMR1_INT

; Timer-1

TMR0_INT

; Timer-0

INT1

; Int.1

INT0

; Int.0

BIT_INT

; BIT

KEY_INT

; Key Scan

RESET

; Reset

ORG

0F000H

;********************************************
;

MAIN PROGRAM *

;********************************************
;
RESET:

;Disable All Interrupts

CLRG
LDX

RAM_CLR:

LDA

;RAM Clear(!0000

->!00BF

)

STA

{X}+

CMPX

#0C0H

BNE

RAM_CLR

;

LDX

#0BFH

;Stack Pointer Initialize

TXSP

;

CALL

LCD_CLR

;Clear LCD display memory

;

LDM

R0, #0

;Normal Port 0

LDM

R0DR,#1000_0010B

;Normal Port Direction

LDM

R0PU,#1000_0010B

;Pull Up Selection Set

LDM

R0CR,#0000_0001B

;R0 port Open Drain control

:
:
LDM

SCMR,#1111_0000B

;System clock control

:
:

GMS81C5108

JUNE 2001 Ver 1.0

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-
ble. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and LCD memory.

Figure 8-8 Data Memory Map

User Memory

The GMS81C5108 has 192

8 bits for the user memory

(RAM).

There are two page internal RAM. Page is selected by G-
flag and RAM page selection register RPR. When G-flag
is cleared to "0", always page 0 is selected regardless of
RPR value. If G-flag is set to "1", page will be selected ac-
cording to RPR value.

Figure 8-9 RAM page configuration

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0

to 0FF

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.

More detailed informations of each register are explained
in each peripheral section.

Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction.

Example; To write at CKCTLR

LDM

CKCTLR,#05H ;Divide ratio

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 20.

LCD Display Memory

LCD display data area is handled in LCD section.

See "19.3 LCD Display Memory" on page 73.

USER MEMORY

(Including STACK Area)

PERIPHERAL CONTROL

REGISTERS

MEMORY

0000

00BF

00C0

00FF

0100

0124

PAGE0

PAGE1

LCD DISPLAY

(192 Bytes)

Page 0

Page 0: 00~FF

Page 1

Page 1: 100~124

RPR=1, G=1

RPR=0, G=0

GMS81C5108

JUNE 2001 Ver 1.0

Address

Register Name

Symbol

R/W

Initial Value

Addressing

Mode

Page

7 6 5 4 3 2 1 0

00C0

R0 port data register

R/W

0 0 0 0 0 0 0 0

byte, bit

00C1

R1 port data register

R/W

0 0 0 0 0 0 0 0

byte, bit

00C2

R2 port data register

R/W

- - - - 0 0 0 0

byte, bit

00C3

R3 port data register

R/W

- - - - 0 0 0 0

byte, bit

00C8

R0 port I/O direction register

R0DR

0 0 0 0 0 0 0 0

byte

00C9

R1 port I/O direction register

R1DR

0 0 0 0 0 0 0 0

byte

00CA

R2 port I/O direction register

R2DR

- - - - 0 0 0 0

byte

00CB

R3 port I/O direction register

R3DR

- - - - 0 0 0 0

byte

00D0

R0 port pull-up register

R0PU

0 0 0 0 0 0 0 0

byte

00D1

R1 port pull-up register

R1PU

0 0 0 0 0 0 0 0

byte

00D2

R2 port pull-up register

R2PU

- - - - 0 0 0 0

byte

00D3

R3 port pull-up register

R3PU

- - - - 0 0 0 0

byte

00D4

R0 port open drain control register

R0CR

0 0 0 0 0 0 0 0

byte

00D5

R1 port open drain control register

R1CR

0 0 0 0 0 0 0 0

byte

00D6

R2 port open drain control register

R2CR

- - - - 0 0 0 0

byte

00D7

R3 port open drain control register

R3CR

- - - - 0 0 0 0

byte

00D8

Ext. interrupt edge selection register

IESR

R/W

- - 0 0 0 0 0 0

byte, bit

00D9

Port selection register

PMR

R/W

- 0 - 0 0 0 0 0

byte, bit

00DA

Interrupt enable low register

IENL

R/W

- 0 0 0 0 - - -

byte, bit

00DB

Interrupt enable high register

IENH

R/W

- 0 0 0 0 0 0 0

byte, bit

00DC

Interrupt request flag low register

IRQL

R/W

- 0 0 0 0 - - -

byte, bit

00DD

Interrupt request flag high register

IRQH

R/W

- 0 0 0 0 0 0 0

byte, bit

00DE

Sleep mode register

SMR

R/W

- - - - - - - 0

byte, bit

00E0

Timer 0 mode register

TM0

R/W

- - 0 0 0 0 0 0

byte, bit

00E1

Timer 0 counter register

0 0 0 0 0 0 0 0

byte, bit

Timer 0 data register

TDR0

1 1 1 1 1 1 1 1

byte

Timer 0 input capture register

CDR0

0 0 0 0 0 0 0 0

byte, bit

00E2

Timer 1 mode register

TM1

R/W

0 0 0 0 0 0 0 0

byte, bit

00E3

Timer 1 data register

TDR1

1 1 1 1 1 1 1 1

byte

PWM0 pulse period register

T1PPR

1 1 1 1 1 1 1 1

byte

00E4

Timer 1 counter register

0 0 0 0 0 0 0 0

byte, bit

Timer 1 input capture register

CDR1

0 0 0 0 0 0 0 0

byte, bit

PWM0 pulse duty register

T1PDR

R/W

0 0 0 0 0 0 0 0

byte, bit

00E5

PWM0 high register

PWMHR

- - - - 0 0 0 0

byte

00EC

A/D converter mode register

ADMR

R/W

- 0 - - 0 0 0 1

byte, bit

00ED

A/D converter data register

ADDR

x x x x x x x x

byte, bit

Table 8-1 Control Registers

GMS81C5108

JUNE 2001 Ver 1.0

00EF

Watch timer mode register

WTMR

R/W

- 0 0 0 0 0 0 0

byte, bit

00F0

Key scan mode register

KSMR

R/W

0 0 0 0 0 0 0 0

byte, bit

00F1

LCD control register

LCR

R/W

0 0 0 0 0 0 0 0

byte, bit

00F3

RAM paging register

RPR

R/W

- - - - - - 0 0

byte, bit

00F4

Basic interval timer register

BITR

0 0 0 0 0 0 0 0

byte, bit

Clock control register

CKCTLR

- - - - 0 1 1 1

byte

00F5

System clock mode register

SCMR

R/W

0 0 0 0 0 0 0 0

byte, bit

00F6

Remocon mode register

RMR

R/W

- 0 0 0 0 0 0 0

byte, bit

00F7

Carrier frequency high selection

CFHS

- - 1 1 1 1 1 1

byte

00F8

Carrier frequency low selection

CFLS

- - 1 1 1 1 1 1

byte

00F9

Remocon data high register

RDHR

1 1 1 1 1 1 1 1

byte

00FA

Remocon data low register

RDLR

1 1 1 1 1 1 1 1

byte

Remocon data counter

RDC

0 0 0 0 0 0 0 0

byte, bit

00FB

Remocon output data register

RODR

R/W

- - - - - - - 0

byte, bit

00FC

Remocon output buffer

ROB

R/W

- - - - - - - 0

byte, bit

00FD

Buzzer data register

BDR

0 0 0 0 0 0 0 0

byte

00FE

Serial I/O mode register

SIOM

R/W

0 0 0 0 0 0 0 1

byte, bit

00FF

Serial I/O data register

SIOD

R/W

x x x x x x x x

byte, bit

1. "byte", "bit" means that register can be addressed by not only bit but byte manipulation instruction.
2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write

instruction such as bit manipulation.

Address

Register Name

Symbol

R/W

Initial Value

Addressing

Mode

Page

7 6 5 4 3 2 1 0

Table 8-1 Control Registers

GMS81C5108

JUNE 2001 Ver 1.0

8.4 Addressing Mode

The GMS81C5108 uses six addressing modes;

· Register addressing

· Immediate addressing

· Direct page addressing

· Absolute addressing

· Indexed addressing

· Register-indirect addressing

(1) Register Addressing

(2) Immediate Addressing

#imm

In this mode, second byte (operand) is accessed as a data
immediately.

Example:

0435

ADC

#35

When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.

Example: G=1, RPR=01

E45535

LDM

,#55

(3) Direct Page Addressing

In this mode, a address is specified within direct page.

Example; G=0

C535

LDA

RAM[35

]

(4) Absolute Addressing

!abs

Absolute addressing sets corresponding memory data to
Data, i.e. second byte (Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

Example;

0735F0

ADC

!0F035

ROM[0F035

]

A+35

MEMORY

0F100

data

0135

0F102

0F101

data

0E551

data

0E550

0F100

data

0F035

0F102

0F101

A+data+C

address: 0F035

GMS81C5108

JUNE 2001 Ver 1.0

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

less of G-flag and RPR.

981501

INC

!0115

ROM[115

]

(5) Indexed Addressing

X indexed direct page (no offset)

{X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15

, G=1, RPR=01

LDA

{X}

;ACC

RAM[X].

X indexed direct page, auto increment

{X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA

Example; G=0, X=35

LDA

{X}+

X indexed direct page (8 bit offset)

dp+X

This address value is the second byte (Operand) of com-
mand plus the data of

-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

C645

LDA

0F100

data

115

0F102

0F101

data+1

data

address: 0115

data

115

0E550

data

36H

data

0E551

data

0E550

+0F5

=13A

GMS81C5108

JUNE 2001 Ver 1.0

Y indexed direct page (8 bit offset)

dp+Y

This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute

!abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.

Example; Y=55

D500FA

LDA

!0FA00

(6) Indirect Addressing

Direct page indirect

[dp]

Assigns data address to use for accomplishing command
which sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL

Example; G=0

3F35

JMP

[35

]

X indexed indirect

[dp+X]

Processes memory data as Data, assigned by 16-bit pair
m e m o r y w h i c h i s d e t e r m i n e d b y p a i r d a t a
[dp+X+1][dp+X] Operand plus

X-register data in Direct

page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

1625

ADC

[25

+X]

0F100

data

0FA55

0FA00

+55

=0FA55

0F102

0F101

jump to address 0E30A

0FA00

0E30A

0E005

0FA00

0E005

data

A + data + C

25 + X(10) = 35

GMS81C5108

JUNE 2001 Ver 1.0

9. I/O PORTS

The GMS81C5108 has seven ports (R0, R1, R2 and R3),
and LCD segment port (SEG0~SEG36), and LCD com-
mon port (COM0~COM3).

These ports pins may be multiplexed with an alternate
function for the peripheral features on the device.

9.1 Registers for Port

Port Data Registers

The Port Data Registers (R0, R1, R2, R3) are represented
as a D-Type flip-flop, which will clock in a value from the
internal bus in response to a "write to data register" signal
from the CPU. The Q output of the flip-flop is placed on
the internal bus in response to a "read data register" signal
from the CPU. The level of the port pin itself is placed on
the internal bus in response to "read data register" signal
from the CPU. Some instructions that read a port activating
the "read register" signal, and others activating the "read
pin" signal.

Port Direction Registers

All pins have data direction registers which can define
these ports as output or input. A "1" in the port direction
register configure the corresponding port pin as output.
Conversely, write "0" to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write "55

" to address 0C8

(R0 port direction reg-

ister) during initial setting as shown in Figure 9-1.

All the port direction registers in the GMS81C5108 have 0
written to them by reset function. On the other hand, its in-
itial status is input.

Figure 9-1 Example of port I/O assignment

Pull-up Control Registers

The R0, R1,R2 and R3 ports have internal pull-up resis-
tors. Figure 9-2 shows a functional diagram of a typical

pull-up port. It is connected or disconnected by Pull-up
Control register (RnPU). The value of that resistor is typi-
cally 100k

. Refer to DC characteristics for more details.

When a port is used as key input, input logic is firmly ei-
ther low or high, therefore external pull-down or pull-up
resisters are required practically. The GMS81C5108 has
internal pull-up, it can be logic high by pull-up that can be
able to configure either connect or disconnect individually
by pull-up control registers RnPU.

When ports are configured as inputs and pull-up resistor is
selected by software, they are pulled to high.

Figure 9-2 Pull-up Port Structure

Open drain port Registers

The R0, R1, R2 and R3 ports have open drain port resistors
R0CR~R3CR.
Figure 9-3 shows an open drain port configuration by control reg-
ister. It is selected as either push-pull port or open-drain port by
R0CR, R1CR, R2CR and R3CR.

Figure 9-3 Open-drain Port Structure

I : INPUT PORT

WRITE "55

" TO PORT R0 DIRECTION REGISTER

R0 DATA

R0 DIRECTION

R1 DATA

R1 DIRECTION

0C0

0C1

0C8

0C9

BIT

PORT

O : OUTPUT PORT

PULL-UP RESISTOR

PORT PIN

1: Connect

0: Disconnect

Pull-up control bit

VDD

GND

VDD

PORT PIN

1: Open drain

0: Push-pull

Open drain port selection bit

GND

GMS81C5108

JUNE 2001 Ver 1.0

9.2 I/O Ports Configuration

R0 Ports

R0 is an 8-bit CMOS bidirectional I/O port (address
0C0

). Each I/O pin can independently used as an input or

an output through the R0DR register (address 0C8

R0 has internal pull-ups that is independently connected or
disconnected by R0PU. The control registers for R0 are
shown below.

In addition, Port R0 and R3 are multiplexed with various
special features. The control register PMR (address 0D9H)
controls the selection of alternate function. After reset, this
value is "0", port may be used as normal I/O port.
To use alternate function such as External Interrupt rather
than normal I/O, write "1" in the corresponding bit of
PMR0.

R1 Ports

R1 is an 8-bit CMOS bidirectional I/O port (address
0C1

). Each I/O pin can independently used as an input or

an output through the R1DR register (address 0C9

R1 has internal pull-ups that is independently connected or
disconnected by register R1PU. If the key scan function is
used, these pin can input the key switch signal without ex-
ternal pull-up registers. For more details refer to "18. KEY
SCAN" on page 70.

The control registers for R1 are shown below.

PWMO (PWM Output)
0: R31 Port
1: PWM

R0 Data Register

ADDRESS : 0C0

RESET VALUE : 00

R07

R06

R05

R04

R03

R02

R01

R00

Port Direction

R0 Direction Register

R0DR

ADDRESS : 0C8

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R0 Pull-up

R0PU

ADDRESS :0D0

RESET VALUE : 00

0: Without pull-up
1: With pull-up

Open Drain select

R0 Open Drain

R0CR

ADDRESS :0D4

RESET VALUE : 00

0: No Open Drain
1: Open Drain

Port Mode Register

PMR

ADDRESS :0D9

RESET VALUE : -0-00000

PWMO

BUZ

EC0

INT2

INT1

INT0

BUZ (Buzzer Output)
0: R04 Port
1: BUZ

EC0 (Timer0 Event Input)
0: R03 Port
1: EC0

INT2 (External Interrupt)
0: R02 Port
1: INT2

INT1 (External Interrupt)
0: R01 Port
1: INT1

INT0 (External Interrupt)
0: R00 Port
1: INT0

Selection Register

Port Pin

Alternate Function

R00
R01
R02
R03
R04
R31

INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
EC0 (Timer0 Event Input)
BUZ (Buzzer Output)
PWM (PWM Output)

R1 Data Register

ADDRESS : 0C1

RESET VALUE : 00

Port Direction

R1 Direction Register

R1DR

ADDRESS : 0C9

RESET VALUE : 00

0: Input
1: Output

Pull-up select

R1 Pull-up

R1PU

ADDRESS : 0D1

RESET VALUE : 00

0: Without pull-up
1: With pull-up

R17

R16

R15

R14

R13

R12

R11

R10

Open Drain select

R1 Open Drain

R1CR

ADDRESS :0D5

RESET VALUE : 00

0: No Open Drain
1: Open Drain

KEY Input select

KEY SCAN Mode Register

KSMR

ADDRESS :0F0

RESET VALUE : 00

0: Port selection
1: KS selection

Selection Register

GMS81C5108

JUNE 2001 Ver 1.0

Port R1 is multiplexed with various special features.The
control registers controls the selection of alternate func-
tion. After reset, this value is "0", port may be used as nor-
mal I/O port. The way to select alternate function such as
comparator input or buzzer will be shown in each periph-
eral section.

In addition, R1 port is used as key scan function which op-
erate with normal input port.

Input or output is configured automatically by each func-
tion register (KSMR) regardless of R1DR.

R2 Port

R2 is a 4-bit CMOS bidirectional I/O port (address 0C2

Each I/O pin can independently used as an input or an out-
put through the R2DR register (address 0CA

R2 has internal pull-ups that is independently connected or
disconnected by R2PU (address 0D2

). The control regis-

ters for R2 are shown as below.

R3 Port

R3 is a 4-bit CMOS bidirectional I/O port (address 0C3

Each I/O pin can independently used as an input or an out-
put through the R3DR register (address 0CB

SEG0~SEG36

Segment signal output pins for the LCD display. See "19.
LCD DRIVER" on page 71 for details.

COM0~COM3

Common signal output pins for the LCD display. See "19.
LCD DRIVER" on page 71 for details.

SEG34~SEG36 and COM1~COM3 are selected by LCDD
of the LCR register.

R2 Data Register

ADDRESS: 0C2

RESET VALUE: ----0000

Port Direction

R2 Direction Register

R2DR

ADDRESS : 0CA

RESET VALUE : ----0000

0: Input
1: Output

Pull-up select

R2 Pull-up

R2PU

ADDRESS : 0D2

RESET VALUE : ----0000

0: Without pull-up
1: With pull-up

R23

R22

R21

R20

Pull-up select

R2 Open Drain

R2CR

ADDRESS : 0D6

RESET VALUE : ----0000

0: No Open Drain
1: Open Drain

Selection Register

R3 Data Register

ADDRESS: 0C3

RESET VALUE: ----0000

Port Direction

R3 Direction Register

R3DR

ADDRESS : 0CB

RESET VALUE : ----0000

0: Input
1: Output

Pull-up select

R3 Pull-up

R3PU

ADDRESS : 0D3

RESET VALUE : ----0000

0: Without pull-up
1: With pull-up

R33

R32

R31

R30

Pull-up select

R3 Open Drain

R3CR

ADDRESS : 0D7

RESET VALUE : ----0000

0: No Open Drain
1: Open Drain

Selection Register

GMS81C5108

JUNE 2001 Ver 1.0

10. CLOCK GENERATOR

As shown in Figure 10-1, the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. Power consumption can
be reduced by switching them to the low power operation
frequency clock can be easily obtained by attaching a res-
onator between the X

and X

OUT

pin and the SX

and

OUT

pin, respectively. The system clock can also be ob-

tained from the external oscillator.

The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware. The internal system clock can be selected
by bit2, and bit3 of the system clock mode register (SC-
MR). The registers are shown in Figure 10-2.

To the peripheral block, the clock among the not-divided
original clocks, divided by

, 4,...,

up to 1024 can be pro-

vided. Peripheral clock is enabled or disabled by STOP in-
struction. The peripheral clock is controlled by clock
control register (CKCTLR). See "11. BASIC INTERVAL
TIMER" on page 43 for details.

Figure 10-1 Block Diagram of Clock Generator

CPU clock

Instruction cycle time

MAIN

= 4MHz

SUB

= 32.768kHz

0.5 us

61 us

2.0 us

244 us

4.0 us

488 us

16.0 us

1953 us

Internal system clock

PRESCALER

Peripheral clock

MUX

128

256

512

1024

select clock

SCS[1:0]

OSC Stop

SYCC<1>

SYCC<0>

STOP Mode

SLEEP Mode

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

** Clock is frozen by STOP or SLEEP[SMR.0] Instruction.
** Clock is released
1) by BIT overflow when previos state has been STOP mode.
2) by interrupts when previos state has been SLEEP mode.

PRES

CAL

(Hz)

PS0

PS3

PS2

PS4

PS1

PS10

PS9

PS5

PS6

PS7

Frequency

period

500K

250K

125K

62.5K

250n

500n

16u

32u

64u

256u

128u

3.906K

7.183K

15.63K

31.25K

PS8

GMS81C5108

JUNE 2001 Ver 1.0

The system clock is decided by bit1 of the system clock
mode register, SCMR. In selection Sub clock, to oscillate
or stop the Main clock is decided by bit0 of SCMR.

On the initial reset, internal system clock is PS1 which is
the fastest and other clock can be provided by bit2 and bit3
of SCMR.

Figure 10-2 SCMR : System Clock Control Registers

R/W

SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)

SCS[1:0] (System clock source select)
00: f

MAIN

01: f

MAIN

INITIAL VALUE: 00

ADDRESS: 0F5

SCMR (System Clock Mode Register)

10: f

MAIN

11: f

MAIN

MSB

LSB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

R/W

SVD[1:0] (SVD Flag)
SVD0 : set at VDD=2.2V
SVD1 : set at VDD=1.7V

SVRT (System Reset Control by SVD1 Bit)
0 : System reset by SVD1 Flag
1 : Don't system reset by SVD1 Flag (Freeze)

SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable

* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.

GMS81C5108

JUNE 2001 Ver 1.0

10.1 Operation Mode

The system clock controller starts or stops the main-fre-
quency clock oscillator and switches between the sub fre-
quency clock. The operating mode is generally divided
into the main active mode and the sub active mode, which
are controlled by System clock mode register (SCMR).
Figure 10-3 shows the operating mode transition diagram.

System clock control is performed by the system clock
mode register, SCMR. During reset, this register is initial-
ized to "0" so that the main-clock operating mode is select-
ed.

Main Active mode

This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the
high-frequency clock. At reset release, this mode is in-
voked.

Sub Active mode

This mode is low-frequency operating mode
In this mode, the CPU and the peripheral hardware clock
are provided by low-frequency clock oscillation, so power
consumption can be reduced.

SLEEP mode

In this mode, the CPU clock stops while peripherals and
the oscillation source continue to operate normally.

STOP mode

In this mode, the system operations are all stopped, holding
the internal states valid immediately before the stop at the
low power consumption level.

Figure 10-3 Operating Mode

Main Active

Mode

Main : Stop or Oscillation (case of **1)
Sub : Oscillation

Main : Oscillation
Sub : Oscillation

Sub Active

Mode 1

Sub Active

Mode 2

Stop / Sleep

Mode

*

No

*
No

System Clock : Main

Main : Oscillation
Sub : Oscillation
System Clock : Sub

SET1 SCMR.1

CLR1 SCMR.1

* No

te1

P /

(**

T1 S

M SCM

SET

R.0

CLR1 SCM

.
0

SET

SCMR.

* Note1 / * Note2

STOP / SET1 SMR.0

System Clock : Stop

Main : Stop
Sub : Oscillation
System Clock : Sub

* Note1 : Stop released by

Reset, Key Scan
Watch Timer interrupt
Timer interrupt (event counter)
SIO (External clock)
External interrupt

* Note2 : Sleep released by

Reset, Key Scan
All interrupts

* Note3 : this is sequential

1) CLR1 SCMR.0
2) Oscillation stabilation time (more than 65ms)
3) CLR1 SCMR.1

- Sub clock cannot be stopped by STOP instruction.

GMS81C5108

JUNE 2001 Ver 1.0

10.2 Operation Mode Switching

In the Main active mode, only the high-frequency clock os-
cillator is used.

In the Sub active mode, the low-frequency clock oscilla-
tion is used, so the low power voltage operation or the low
power consumption operation can be enabled. Instruction
execution does not stop during the change of operation
mode. In this case, some peripheral hardware capabilities
may be affected. For details, refer to the description of the
relevant operation.

The following describes the switching between the Main
active mode and the Sub active mode. During reset, the
system clock mode register is initialized at the Main active
mode. It must be set to the Sub active mode for reducing
the power consumption.

Switching from Main active to Sub active

First, write "02

into lower 2 bits of SCMR to switch the

main system clock to the sub-frequency clock.
Next, write "03

to turn off main frequency oscillation.

Example:

:
:
:
LDM SCMR,#02

;Switch to sub active

LDM SCMR,#03

;Turn off main clock

:
:

Returning from Sub active to Main active

First, write "02

into lower 2 bits of the SCMR to turn on

the main-frequency oscillation. This time, the stabilization
(warm-up) time needs to be taken by the software delay
routine. Sub active mode can also be released by setting the
RESET pin to low, which immediately performs the reset
operation. After reset, the GMS81C5108 is placed in Main
active mode.

Example:

:
:
:
LDM SCMR,#02

;Turn on main-clock

CALL DELAY ;Wait until stable
LDM SCMR,#0 ;Move to main active

:
:
:

;about 65ms software delay
DELAY:

LDA

DELAY0:

INC

CMP

#85H

BCC

DELAY0

RET

Shifting from the Normal operation to the SLEEP
mode

By setting bit 0 of SMR, the CPU clock stops and the
SLEEP mode is invoked. The CPU stops while other pe-
ripherals are operate normally.

The way of release from this mode is RESET and all avail-
able interrupts.

For more detail, See " SLEEP Mode" on page 39

Shifting from the Normal operation to the STOP
mode

By executing STOP instruction, the main-frequency clock
oscillation stops and the STOP mode is invoked. But sub-
frequency clock oscillation is operated continuously.
After the STOP operation is released by reset, the opera-
tion mode is changed to Main active mode.

The methods of release are RESET, Key scan interrupt,
Watch Timer interrupt, Timer/Event counter1 (EC0 pin),
SIO (External clock) and External Interrupt.

For more details, see " STOP Mode" on page 40.

Note: In the STOP and SLOW operating modes, the power
consumption by the oscillator and the internal hardware is
reduced. However, the power for the pin interface (depend-
ing on external circuitry and program) is not directly associ-
ated with the low-power consumption operation. This must
be considered in system design as well as interface circuit
design.

GMS81C5108

JUNE 2001 Ver 1.0

10.3 Power Saving Operation

GMS81C5108 has 2 power-saving mode. In power-saving
mode, power consumption is reduced considerably that in
Battery operation Battery life can be extended a lot.

Sleep mode is entered by setting bit 0 of Sleep Mode Reg-
ister (SMR), and STOP Mode is entered by STOP instruc-
tion.

SLEEP Mode

In this mode, the internal oscillation circuits remain active.

Oscillation continues and peripherals are operate normally
but CPU stops. Movement of all Peripherals is shown in
Table 10-1. Sleep mode is entered by setting bit 0 of SMR
(address 0DE

It is released by RESET or interrupt. To be released by in-
terrupt, interrupt should be enabled before Sleep mode.

Figure 10-5 SLEEP Mode Register

Figure 10-6 Sleep Mode Release Timing by External Interrupt

Figure 10-7 SLEEP Mode Release Timing by RESET pin

Sleep Mode Register

SMR

ADDRESS : 0DE

RESET VALUE : -------0

0: Release Sleep Mode
1: Enter Sleep Mode

Oscillator

Normal Operation

Stand-by Mode

Normal Operation

Interrupt

Internal CPU Clock

Release

Set bit 0 of SMR

or SX

pin)

Oscillator

or SX

pin)

BIT Counter

= 62.5ms

RESET

Internal CPU Clock

Clear & Start

Normal Operation

Stand-by Mode

Normal Operation

Release

Set bit 0 of SMR

~~
~~

at 4.19MHz by hardware

x 256

MAIN

1024

GMS81C5108

JUNE 2001 Ver 1.0

STOP Mode

For applications where power consumption is a critical
factor, device provides STOP mode for reducing power
consumption.

Start The Stop Operation

The STOP mode can be entered by STOP instruction dur-

ing program execution. In Stop mode, the on-chip main-
frequency oscillator, system clock, and peripheral clock
are stopped (Watch timer clock is oscillating continuous-
ly:. With the clock frozen, all functions are stopped, but the
on-chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.

Table 10-2 Clock Operation of STOP and SLEEP mode

Note: Since the X

pin is connected internally to GND to

avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.

In the Stop mode of operation, V

can be reduced to min-

imize power consumption. Be careful, however, that V

is not reduced before the Stop mode is invoked, and that
V

is restored to its normal operating level before the

Stop mode is terminated.

The reset should not be activated before V

is restored to

its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP in-
struction should be written as shown in example below.

Peripheral

STOP Mode

Sleep Mode

CPU

All CPU operations are disabled

RAM

Retain

LCD driver

Operates continuously

Basic Interval Timer

Halted

Operates continuously

Timer/Event counter 0,1

Halted (Only when the Event counter mode
is enabled, Timer 0,1 operates normally)

Timer/Event counter 0,1 operates continuously

Watch Timer

Operates continuously

Key Scan

Active

Main-oscillation

Stop (X

=L, X

OUT

=L)

Oscillation

Sub-oscillation

Oscillation

I/O ports

Retain

Control Registers

Retain

Release method

by RESET, Key Scan interrupt,
SIO interrupt, Watch Timer interrupt,
Timer interrupt (EC0), and External interrupt

by RESET, All interrupts

Table 10-1 Peripheral Operation during Power Saving Mode

1. refer to the Table 10-2

Operating

Clock source

Main

Operating Mode

Main

Sleep Mode

Sub

Operating Mode

Sub

Sleep Mode

Stop Mode

Main Clock

Oscillation

SCMR<1:0>

00,01,10

Oscillation

Stop

SCMR<1:0>

00,01,10

Oscillation

Stop

Sub Clock

Oscillation

System Clock

Active

Stop

Active

Stop

Peri. Clock

Active

Stop

GMS81C5108

JUNE 2001 Ver 1.0

Example)

:
LDM

CKCTLR,#0000_1111B

STOP
NOP
NOP
:

The Interval Timer Register CKCTLR should be initial-
ized by software in order that oscillation stabilization time
should be longer than 20ms before STOP mode.

Release the STOP mode

The exit from STOP mode is using hardware reset or exter-
nal interrupt, watch timer, SIO interrupt, key scan or timer
interrupt (EC0).

To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event counter, EC0
pin can release it by Timer/Event counter

Interrupt re-

quest

Reset redefines all the control registers but does not change
the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.

Start-up is performed to acquire the time for stabilizing os-
cillation. During the start-up, the internal operations are all
stopped.

Figure 10-8 STOP Mode Release Timing by External Interrupt

Figure 10-9 STOP Mode Release Timing by RESET

Before executing Stop instruction, Basic Interval Timer must be set

Oscillator

pin)

BIT Counter

n+1

n+2

n+3

Normal Operation

Stop Operation

Normal Operation

20ms

External Interrupt

Internal Clock

Clear

STOP Instruction
Executed

properly by software to get stabilization time which is longer than 20ms.

by software

Oscillator

pin)

BIT Counter

n+1

n+2

n+4

Normal Operation

Stop Operation

Normal Operation

> 62.5ms

Internal Clock

Clear

STOP Instruction

Executed

at 4.19MHz by hardware

RESET

n+3

x 256

MAIN

1024

GMS81C5108

JUNE 2001 Ver 1.0

Minimizing Current Consumption

The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.

Note: In the STOP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(V

); however, when the input level becomes higher

than the power voltage level (by approximately 0.3V), a cur-
rent begins to flow. Therefore, if cutting off the output tran-
sistor at an I/O port puts the pin signal into the high-
impedance state, a current flow across the ports input tran-
sistor, requiring it to fix the level by pull-up or other means.

It should be set properly that current flow through port
doesn't exist.

First consider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn't
flow.

But input voltage level should be V

or V

. Be careful

that if unspecified voltage, i.e. if unfirmed voltage level
(not V

or V

) is applied to input pin, there can be little

current (max. 1mA at around 2V) flow.

If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to High, and if there
is external pull-saving register, it is set to low.

Figure 10-10 Application Example of Unused Input Port

Figure 10-11 Application Example of Unused Output Port

INPUT PIN

GND

Weak pull-up current flows

internal
pull-up

INPUT PIN

Very weak current flows

OPEN

i=0

GND

When port is configured as an input, input level should
be closed to 0V or V

to avoid power consumption.

OUTPUT PIN

GND

In the left case, much current flows from port to GND.

OFF

OUTPUT PIN

GND

In the left case, Tr. base current flows from port to GND.

i=0

OFF

OPEN

GND

OFF

To avoid power consumption, there should be low output

OFF

to the port.

GMS81C5108

JUNE 2001 Ver 1.0

11. BASIC INTERVAL TIMER

The GMS81C5108 has one 8-bit Basic Interval Timer that
is free-run and can not stop. Block diagram is shown in
Figure 11-1.

The Basic Interval Timer Register (BITR) is increased ev-
ery internal count pulse which is divided by prescaler.
Since prescaler has divided ratio by 8 to 1024, the count
rate is 1/8 to 1/1024 of the oscillator frequency. After reset,
the BCK bits are all set, so the longest oscillation stabiliza-
tion time is obtained.

It also provides a Basic interval timer interrupt (BITF).
The count overflow of BITR from FF

to 00

causes the

interrupt to be generated. The Basic Interval Timer is con-
trolled by the clock control register (CKCTLR) shown in
Figure 11-2.

Source clock can be selected by lower 3 bits of CKCTLR.
When write "1" to bit BCL of CKCTLR, BITR register is
cleared to "0" and restart to count up. The bit BCL be-
comes "0" automatically after one machine cycle by hard-
ware.

BITR and CKCTLR are located at same address, and ad-
dress 0F4

is read as a BITR, and written to CKCTLR.

Figure 11-1 Block Diagram of Basic Interval Timer

Table 11-1 Basic Interval Timer Interrupt Time

MUX

Basic Interval Timer Interrupt

BITR

Select Input clock

Basic Interval Timer

source
clock

8-bit up-counter

BCK<2:0>

BCL

MAIN

or f

SUB

MAIN

or f

SUB

MAIN

or f

SUB

MAIN

or f

SUB

MAIN

or f

SUB

MAIN

or f

SUB

MAIN

or f

SUB

MAIN

or f

SUB

CKCTLR

clear

overflow

Internal bus line

clock control register

[0F4

]

[0F4

]

BITF

MAIN

: main-clock frequency

SUB

: sub-clock frequency

BCK

<2:0>

Source clock

Interrupt (overflow) Period

SC M R [1:0]=

00 or 01

SC M R [1:0]=

10 or 11

At f

MAIN

=4MHz

At f

SUB

=32.768kHz

000

001

010

011

100

101

110

111

MAIN

SUB

0.512

1.024

2.048

4.096

8.192

16.384

32.768

65.536

62.5

125.0

250.0

500.0

1000.0

2000.0

4000.0

8000.0

GMS81C5108

JUNE 2001 Ver 1.0

Figure 11-2 BITR: Basic Interval Timer Mode Register

Example 1:

Interrupt request flag is generated every 8.192ms at 4MHz.

:
LDM

CKCTLR,#0CH

SET1

BITE

EI
:

BCL

BCK1

Basic Interval Timer source clock select
000: f

MAIN

001: f

MAIN

010: f

MAIN

011: f

MAIN

100: f

MAIN

101: f

MAIN

110: f

MAIN

111: f

MAIN

Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically

INITIAL VALUE: ----0111

ADDRESS: 0F4

after one machine cycle.

CKCTLR

INITIAL VALUE: 00

ADDRESS: 0F4

BITR

Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.

Caution:

8-BIT BINARY COUNTER

MAIN

: main-clock frequency

SUB

: sub-clock frequency

BCK0

BCK2

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

GMS81C5108

JUNE 2001 Ver 1.0

12. Timer / Counter

Timer/Event Counter consists of prescaler, multiplexer, 8-
bit timer data register, 8-bit counter register, mode register,
input capture register and Comparator as shown in Figure
12-3. And the PWM high register for PWM is consisted
separately.

The timer/counter has seven operating modes.
- 8 Bit Timer/Counter Mode
- 8 Bit Capture Mode
- 8 Bit Compare Output Mode
- 16 Bit Timer/Counter Mode
- 16 Bit Capture Mode
- 16 Bit Compare Output Mode
- PWM Mode

In the "timer" function, the register is increased every in-
ternal clock input. Thus, one can think of it as counting in-

ternal clock input. Since a least clock consists of 2 and
most clock consists of 1024 oscillator periods, the count
rate is 1/2 to 1/1024 of the oscillator frequency in Timer0.
And Timer1 can use the same clock source too. In addition,
Timer1 has more fast clock source (1/1 to 1/8).

In the "counter" function, the register is increased in re-
sponse to a 0-to-1 (rising edge) transition at its correspond-
ing external input pin EC0 (Timer 0).

In addition the "capture" function, the register is increased
in response external interrupt same with timer function.
When external interrupt edge input, the count register is
captured into capture data register CDRx.

Timer1 is shared with "PWM" function and "Compare
output" function.

Example 1:

Timer 0 = 8-bit timer mode, 8ms interval at 4MHz
Timer 1 = 8-bit timer mode, 4ms interval at 4MHz

LDM SCMR,#0 ;Main clock mode
LDM TDR0,#249
LDM TM0,#0001_0011B
LDM TDR1,#124
LDM TM1,#0000_1111B

SET1 T0E
SET1 T1E
EI
:
:
:

Example 2:

Timer0 = 16-bit timer mode, 0.5s at 4MHz

LDM SCMR,#0 ;Main clock mode
LDM TDR0,#23H
LDM TDR1,#0F4H
LDM TM0,#0FH ;F

MAIN

/32, 8us

LDM TM1,#4CH

SET1 T0E
EI
:
:
:

Example 3:

Timer0 = 8-bit event counter, 2ms interval at 4MHz
Timer1 = 8-bit capture mode, 2us sampling count.

LDM TDR0,#99 ;99+1, 100 count
LDM TM0,#01FH ;event counter
LDM R0DR,#XXXX_1XXXB ;R03input

LDM IESR,#XXXX_01XXB ;FALLING
LDM PMR,#XXXX_1X1XB ;EC0,INT1
LDM TDR1,#0FFH
LDM TM1,#0001_1011B ;2us

SET1 T0E;ENABLE TIMER 0
SET1 T1E;ENABLE TIMER 1
SET1 INT1E;ENABLE EXT. INT1
EI
:

X: don't care.

Example 4:

Timer0 = 16-bit capture mode, 8us sampling count. at 4MHz

LDM TDR0,#0FFH
LDM TDR1,#0FFH
LDM TM0,#02FH
LDM TM1,#04FH

LDM IESR,#XXXX_XX01B
LDM PMR,#XXXX_XXX1B ;AS INT0

SET1 T0E;ENABLE TIMER 0
SET1 INT0E;ENABLE EXT. INT0
EI
:

X: don't care.

GMS81C5108

JUNE 2001 Ver 1.0

Figure 12-1 Timer0,1 Registers

T0CK2

Bit : 7 6 5 4 3 2 1 0

CAP0

T0CK[2:0] (Timer 0 Input Clock Selection)

111: External Event clock (EC0)

T0CN (Timer 0 Continue Start)
0: Stop Counting
1: Start Counting

T0ST (Timer 0 Start Control)
0: stop counting
1: clear the counter and start count again

Reserved

INITIAL VALUE:--000000

ADDRESS: 0E0

TM0 (Timer0 Mode Register)

R/W

T0CN

T0ST

T0CK1

T0CK0

R/W

CAP0 (Capture Mode Selection Bit)
0: Capture Disable
1: Capture Enable

CAP1

Bit : 7 6 5 4 3 2 1 0

PWME

T1CK[1:0] (Timer 1 Input Clock Selection)

11: Timer 0 Clock

T1CN (Timer 1 Continue Start)
0: Stop Counting
1: Start Counting

T1ST (Timer 1 Start Control)
0: stop counting
1: clear the counter and start count again

INITIAL VALUE:00000000

ADDRESS: 0E2

TM1 (Timer1 Mode Register)

R/W

T1CN

T1ST

T1CK1

T1CK0

R/W

POL (PWM Output Polarity Selection)
0: Duty Active Low
1: Duty Active High

POL

16BIT

R/W

CAP1 (Capture Mode Selection Bit)
0: Capture Disable
1: Capture Enable

PWME (PWM Enable Bit)
0: PWM Disable
1: PWM Enable

16BIT (16 Bit Mode Selection)
0: 8-Bit Mode
1: 16-Bit Mode

**The counter will be cleared and restarted only when the TxST bit cleared and set again.

If TxST bit set again when TxST bit is set, the counter can't be cleared but only start again.

000: f

MAIN

001: f

MAIN

010: f

MAIN

011: f

MAIN

100: f

MAIN

101: f

MAIN

110: f

MAIN

: main-clock frequency

SUB

: sub-clock frequency

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

00: f

MAIN

01: f

MAIN

10: f

MAIN

or f

SUB

or f

SUB

or f

SUB

GMS81C5108

JUNE 2001 Ver 1.0

Figure 12-2 Related Registers with Timer/Counter

CDR0 (Input Capture Register)
T0 (Timer 0 Counter Register)

CDR04

Bit : 7 6 5 4 3 2 1 0

CDR05

INITIAL VALUE:00H

ADDRESS: E1

CDR01

CDR00

CDR03

CDR02

In Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.

CDR07

CDR06

TDR0 (Timer 0 Data Register)

TDR04

Bit : 7 6 5 4 3 2 1 0

TDR05

INITIAL VALUE:FF

ADDRESS: 0E1

TDR01

TDR00

TDR03

TDR02

If the counter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.

TDR07

TDR06

CDR1 (Input Capture Register)
T1 (Timer 1 Counter Register)

CDR14

Bit : 7 6 5 4 3 2 1 0

CDR15

INITIAL VALUE:00

ADDRESS: 0E4

CDR11

CDR10

CDR13

CDR12

In Timer mode, this register is the value of Timer 1 counter and in Capture mode, this register is the value of input capture.

CDR17

CDR16

TDR1 (Timer 1 Data Register)

TDR14

Bit : 7 6 5 4 3 2 1 0

TDR15

INITIAL VALUE:FF

ADDRESS: 0E3

TDR11

TDR10

TDR13

TDR12

If the counter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.

TDR17

TDR16

T1PPR (Timer 1 Pulse Period Register)

T1PPR4

Bit : 7 6 5 4 3 2 1 0

T1PPR5

INITIAL VALUE:FF

ADDRESS: 0E3

T1PPR1 T1PPR0

T1PPR3 T1PPR2

The period is decided by PWM.

T1PPR7 T1PPR6

T1PDR (Timer 1 Pulse Duty Register)

T1PDR4

Bit : 7 6 5 4 3 2 1 0

T1PDR5

INITIAL VALUE:00

ADDRESS: 0E4

W/R

T1PDR1 T1PDR0

T1PDR3 T1PDR2

W/R

In PWM mode, decide the pulse duty.

T1PDR7 T1PDR6

W/R

PWMHR (PWM High Register)

Bit : 7 6 5 4 3 2 1 0

INITIAL VALUE:----0000

ADDRESS: 0E5

PWM01

PWM00

PWM03 PWM02

PWM Period = [PWMHR[3:2] + T1PPR] x Source Clock

Reserved

PWM Duty = [PWMHR[1:0] + T1PDR] x Source Clock

GMS81C5108

JUNE 2001 Ver 1.0

Table 12-1 Operating Modes of Timer 0 and Timer 1

12.1 8-Bit Timer/Counter Mode

The GMS81C5108 has two 8-bit Timer/Counters, Timer 0,
Timer 1, as shown in Figure 12-3.

The "timer" or "counter" function is selected by mode reg-
isters TMx as shown in Figure 12-1 and Table 12-1. To use

as an 8-bit timer/counter mode, bit CAP0 of TM0 is
cleared to "0" and bits 16BIT of TM1 should be cleared to
"0" (Table 12-1 ).

Figure 12-3 Block Diagram of Timer/Event Counter

16BIT

CAP0

CAP1

PWME

T0CK[2:0]

T1CK[1:0]

PWMO

Timer 0

Timer 1

XXX

8 Bit Timer

111

8 Bit Event Counter

8 Bit Capture

XXX

8 Bit Capture

8 Bit Compare Output

XXX

8 Bit Timer/Counter

10 Bit PWM

XXX

16 Bit Timer

111

16 Bit Event Counter

XXX

16 Bit Capture

XXX

16 Bit Compare Output

X: The value "0" or "1" corresponding your operation

TM0

ADDRESS : 0E0

RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : 0E2

RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

128

512

EC0

Edge Detector

MUX

T0 (8-bit)

TDR0 (8-bit)

T0IF

CLEAR

COMPARATOR

TIMER 0
INTERRUPT

T1 (8-bit)

TDR1 (8-bit)

T1IF

CLEAR

COMPARATOR

TIMER 1
INTERRUPT

T0ST

0 : Stop
1 : Clear and Start

T1ST

0 : Stop
1 : Clear and Start

T0CN

T1CN

T0CK[2:0]

T1CK[1:0]

F/F

COMPO PIN (R31)

1024

X : The value "0" or "1" corresponding your operation.

PWMO

[PMR.6]

SCMR[1:0]

GMS81C5108

JUNE 2001 Ver 1.0

These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 1024 (selected by con-
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
ister TM1).

In the Timer, timer register T

increases from 00

until it

matches TDR

and then reset to 00

. If the value of T

equal with TDR

, Timer

interrupt is occurred (latched in

IF bit). TDR0 and T0 register are in same address, so

this register is read from T0 and written to TDR0.

In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit R03 of the R0 Direction Register (R0DR)
should be set to "0" and the bit EC0 of Port Mode Register
(PMR) should set to "1". The Timer 0 can be used as a
counter by pin EC0 input, but Timer 1 can not used as a
counter.

Note: The contents of TDR0 and TDR1 must be initialized

(by software) with the value between 1

and 0FF

not 0

Figure 12-4 Counting Example of Timer Data Registers

Figure 12-5 Timer Count Operation

Timer 0 (T0IF)
Interrupt

TDR0

TIME

Occur interrupt

Interrupt period

-c

n-1

= P

x (n+1)

Timer 0 (T0IF)
Interrupt

TDR0

TIME

Occur interrupt

stop

clear & start

disable

enable

Start & Stop

T0ST

T0CN
Control count

-c

T0ST = 0

T0ST = 1

T0CN = 0

T0CN = 1

GMS81C5108

JUNE 2001 Ver 1.0

12.2 16 Bit Timer/Counter Mode

The Timer register is running with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000

until it

matches TDR0, TDR1 and then resets to 0000

. The

match output generates Timer 0 interrupt not Timer 1 in-
terrupt.

The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.

In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to "1" respectively.

Figure 12-6 16-bit Timer / Counter Mode

12.3 8-Bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 12-7.

As mentioned above, not only Timer 0 but Timer 1 can also
be used as a capture mode.

The Timer/Counter register is increased in response inter-
nal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1) increases and matches TDR0
(TDR1).

This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.

For example, in Figure 12-9, the pulse width of captured
signal is wider than the timer data value (FF

) over 2

times. When external interrupt is occurred, the captured
value (13

) is more little than wanted value. It can be ob-

tained correct value by counting the number of timer over-

flow occurrence.

Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.

It has three transition modes: "falling edge", "rising edge",
"both edge" which are selected by interrupt edge selection
register IESR (Refer to External interrupt section). In addi-
tion, the transition at INTx pin generate an interrupt.

Note: The CDR0, TDR0 and T0 are in same address. In

the capture mode, reading operation is read the
CDR0 and in timer mode, reading operation is read
the T0. TDR0 is only for writing operation.
The CDR1, T1 are in same address, the TDR1 is lo-
cated in different address. In the capture mode,
reading operation is read the CDR1

TM0

ADDRESS : 0E0

RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : 0E2

RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

128

512

EC0

Edge Detector

MUX

T1 (8-bit)

TDR1 (8-bit)

T0IF

CLEAR

COMPARATOR

TIMER 0

INTERRUPT

T 0 (8 -b it)

TDR0 (8-bit)

T0ST

0 : Stop
1 : Clear and Start

T0CN

T0CK[2:0]

F/F

COMPO (R31)

1024

X : The value "0" or "1" corresponding your operation.

SCMR[1:0]

PWMO

[PMR.6]

GMS81C5108

JUNE 2001 Ver 1.0

Figure 12-7 8-bit Capture Mode

TM0

ADDRESS : 0E0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : 0E2H
RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

128

512

EC0

Edge Detector

MUX

T0 (8-bit)

CDR0 (8-bit)

T0IF

CLEAR

COMPARATOR

TIMER 0
INTERRUPT

T0ST

0 : Stop
1 : Clear and Start

T0CN

T1CN

T0CK[2:0]

T1CK[1:0]

TDR0 (8-bit)

INT0IF

INT 0
INTERRUPT

INT0

T1 (8-bit)

CDR1 (8-bit)

T1IF

CLEAR

COMPARATOR

TIMER 1
INTERRUPT

TDR1 (8-bit)

INT1IF

INT 1
INTERRUPT

INT1

T0ST

0 : Stop
1 : Clear and Start

IESR[1:0]

IESR[3:2]

CAPTURE

1024

SCMR[1:0]

GMS81C5108

JUNE 2001 Ver 1.0

12.4 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except
that the Timer register is running with 16 bits.

The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.

In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to "1" respectively.

Figure 12-10 16-bit Capture Mode

12.5 8-Bit (16-Bit) Compare OutPut Mode

The GMS81C5108 has a function of Timer Compare Out-
put. To pulse out, the timer match can goes to port pin
(R31) as shown in Figure 12-3 and Figure 12-6. Thus,
pulse out is generated by the timer match. These operation
is implemented to pin, R31/PWM.

In this mode, the bit PWMO of Port Mode Register (PMR)
should be set to "1", and the bit PWME of Timer1 Mode
Register (TM1) should be cleared to "0".

In addition, 16-bit Compare output mode is available, also.

This pin output the signal having a 50 : 50 duty square
wave, and output frequency is same as below equation.

12.6 PWM Mode

The GMS81C5108 has one high speed PWM (Pulse Width
Modulation) function which shared with Timer1.

In PWM mode, the R31/PWM pin operates as a 10-bit res-
olution PWM output port. For this mode, the bit PWM of
Port Mode Register (PMR) and the bit PWME of timer1
mode register (TM1) should be set to "1" respectively.

The period of the PWM output is determined by the
T1PPR (PWM Period Register) and PWMHR[3:2] (bit3,2

of PWM High Register) and the duty of the PWM output
is determined by the T1PDR (PWM Duty Register) and
PWMHR[1:0] (bit1,0 of PWM High Register).

The user can use PWM data by writing the lower 8-bit pe-
riod value to the T1PPR and the higher 2-bit period value
to the PWMHR[3:2]. And the duty value can be used with
the T1PDR and the PWMHR[1:0] in the same way.

The T1PDR is configured as a double buffering for glitch-

TM0

ADDRESS : 0E0H
RESET VALUE : --000000

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T0ST

TM1

ADDRESS : 0E2H
RESET VALUE : 00000000

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

128

512

EC0

Edge Detector

MUX

T0 + T1 (16-bit)

TDR1

T0IF

CLEAR

COMPARATOR

TIMER 0

INTERRUPT

T0ST

0 : Stop
1 : Clear and Start

T0CN

T0CK[2:0]

TDR0

INT0IF

INT 0
INTERRUPT

INT0

IESR[1:0]

CAPTURE

CDR1

CDR0

(8-bit)

1024

X : The value "0" or "1" corresponding your operation.

SCMR[1:0]

COMP

Oscillation Frequency

Prescaler Value

TDR

)

(

--------------------------------------------------------------------------------------

GMS81C5108

JUNE 2001 Ver 1.0

less PWM output. In Figure 12-11, the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle).

The bit POL0 of TM1 decides the polarity of duty cycle.

The duty value can be changed when the PWM outputs.
However the changed duty value is output after the current
period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-13. As it were, the absolute duty time is not
changed in varying frequency.

Note: If the user need to change mode from the Timer1

mode to the PWM mode, the Timer1 should be
stopped firstly, and then set period and duty register
value. If user writes register values and changes
mode to PWM mode while Timer1 is in operation,
the PWM data would be different from expected
data in the beginning.

The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.

PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock

PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock

If it needed more higher frequency of PWM, it should be
reduced resolution.

Note: If the duty value and the period value are same, the

PWM output is determined by the bit POL0 (1: High,
0: Low). And if the duty value is set to "00

, the

PWM output is determined by the bit POL0(1: Low,
0: High). The period value must be same or more
than the duty value, and 00

cannot be used as the

period value.

Table 12-2 PWM Frequency vs. Resolution at 4MHz

Figure 12-11 PWM Mode

Resolution

Frequency

T1CK[1:0]

=00 (250nS)

T1CK[1:0]

=01 (500nS)

T1CK[1:0]

=10 (2uS)

10-bit

3.9KHz

1.95KHz

0.49KHZ

9-bit

7.8KHz

3.9KHz

0.98KHZ

8-bit

15.6KHz

7.8KHz

1.95KHz

7-bit

31.25KHz

15.6KHz

3.90KHz

PWMHR

ADDRESS : 0E5

RESET VALUE : ----0000

PWM03

PWM02

PWM01

PWM00

MUX

T1CN

T1CK[1:0]

T1 (8-bit)

T1ST

0 : Stop
1 : Clear and Start

CLEAR

COMPARATOR

T1PDR (8-bit)

PWMHR[1:0]

T1PPR (8-bit)

PWMHR[3:2]

T1PDR (8-bit)

POL

PWMO

R31/PWM

T0 clock source

TM1

ADDRESS : 0E2

RESET VALUE : 00

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

[PMR.6]

Period High

Duty High

Slave

Master

Bit Manipulation Not Available

X : The value "0" or "1" corresponding your operation.

SCMR[1:0]

GMS81C5108

JUNE 2001 Ver 1.0

Figure 12-12 Example of PWM at 4MHz

Figure 12-13 Example of Changing the Period in Absolute Duty Cycle (@4MHz)

Example:

Timer1 @4Mhz,

4kHz -

duty PWM mode

LDM R3DR,#0000_XX1XB ;R31 output
LDM TM1,#0010_0000B ;pwm enable
LDM T1PWHR,#0000_1100B ;20% duty
LDM T1PPR,#1110_0111B ;period 250uS
LDM T1PDR,#1100_0111B ;duty 50uS
LDM RSR,#X1XX_XXXXB ;set pwm port.
LDM TM1,#0010_0011B ;timer1 start

X means don't care

fxin

PWM

3FF

POL=1

PWM
POL=0

Duty Cycle [80

+1 x 250nS = 32.25uS]

Period Cycle [3FF

x 250nS = 256uS, 3.9kHz]

PWMHR = 0C

T1PPR = FF

T1PDR = 80

T1CK[1:0] = 00 (250nS)

PWM03

PWM02

PWM01

PWM00

T1PPR (8-bit)

T1PDR (8-bit)

Period

Duty

Source

PWM
POL=1

Duty Cycle

Period Cycle [0D

+1 x 2uS = 28uS, 35.7kHz]

P W M H R = 0 0

T 1P P R = 0 D

T 1P D R = 0 4

T 1C K [1 :0 ] = 1 0 (2 uS )

00 01

0A 0B 0C 0D 00 01 02

05 06

02 03

[04

+1 x 2uS = 10uS]

Duty Cycle

[04

+1 x 2uS = 10uS]

Period Cycle [09

+1 x 2uS = 20uS, 50kHz]

Duty Cycle

[04

+1 x 2uS = 10uS]

Write T1PPR to 09

Period changed

clock

GMS81C5108

JUNE 2001 Ver 1.0

13. Watch Timer/Watch Dog Timer

This has two functions, one is the interrupt occurrence for
watch time and the other is the signal generation of

WDTOUTB for watch dog.

13.1 Watch Timer

The watch timer consists of the clock selector, 21-bit bina-
ry counter and watch timer mode register. It is a multi-pur-
pose timer. It is generally used for watch design.

The bit 1,2 of WTMR select the clock source of watch tim-
er among sub-clock,

MAIN

of main-clock and

MAIN

main-clock. The

MAIN

of main-clock is used usually for

watch timer test, so generally it is not used for the clock
source of watch timer. The

MAIN

of main-clock is used

when the single clock system is organized. In

MAIN

clock source, if the CPU enters into stop mode, the main-
clock is stopped and then watch timer is also stopped. If the
sub-clock is the source clock, the watch timer count cannot
be stopped. Therefore, the sub-clock does not stop but con-
tinues to oscillate even when the CPU is in the STOP
mode. The timer counter consists of 21-bit binary counter
and it can count to max 64 seconds at sub-clock.

The bit 2, 3 of WTMR select the interrupt request interval
of watch timer among 2Hz, 4Hz, 16Hz and 1/64Hz.

Figure 13-1 Watch Timer Mode Register

Figure 13-2 Watch Timer Block Diagram

WDTCL

Bit : 7 6 5 4 3 2 1 0

WDTEN

WTIN[1:0] (Watch Timer Interrupt Interval Selection)
00: 16Hz
01: 4Hz
10: 2Hz
11: 1/64Hz

WDTEN (Watch Dog Timer Enable Bit)
0: Watch Dog Timer Disable
1: Watch Dog Timer Enable

INITIAL VALUE:-0000000

ADDRESS: 0EF

WTMR (Watch Timer Mode Register)

R/W

WTCK1

WTCK0

WTIN1

WTIN0

R/W

WTEN (Watch Timer Enable Bit)
0: Watch Timer Disable
1: Watch Timer Enable

WTEN

R/W

WTCK[1:0] (Watch Timer Clock Source Selection)
00: Sub. Clock (f

SUB

)

WDTCL (Watch Dog Timer Clear Bit)
0: Timer running
1: WDT Clear (Auto reset after 1 cycle)

01: Main Clock (f

MAIN

)

10: Main Clock (f

MAIN

)

11: -

* When f

SUB

= 32.768 kHz and f

MAIN

= 4.19 MHz

MUX

SUB

WDTCL

MAIN

21 BIT

2 Bit

16 Hz

Watch Timer

MAIN

÷
÷
÷
÷

WTCK[1:0]

Binary Counter

4 Hz
2 Hz

1/64 Hz

MUX

WTIN[1:0]

WTEN

WTIF

Interrupt

F/F

WDTEN

WDTOUT

GMS81C5108

JUNE 2001 Ver 1.0

13.2 Watch Dog Timer

The watch dog timer (WDT) function is used for checking
program malfunction. If the watch dog timer is not reset in
a fixed time, the WDTOUTB pin outputs a low signal.
Therefore, by connecting the WDTOUTB pin and the reset
pin externally, the MCU can be reset when the malfunction
is occurred.

Usually the stop mode is used to reduce the power con-
sumption. When the stop mode is released by watch timer
interrupt, it is recommend to set the WDTCL to clear the
2-Bit counter and enter the stop mode. If the clock source
is 1/64Hz, the WDTCL cannot be cleared in 500ms. In this
case, the user should disable the WDT by clearing the
WDTEN or disconnect the WDTOUTB pin and reset pin.

Usage of Watch Timer in STOP Mode

When the system is off and the watch should be kept work-
ing, follow the steps below.

1. Determines which mode is to be performed between

main mode and sub mode when the MCU is released
from Stop mode and set the clock source of watch timer
to sub-clock.

2. Enters in STOP mode.

3. After released by watch timer interrupt, counts up timer

and refreshes LCD Display. When the performing count
up and refresh the LCD, the CPU operates either in main
frequency mode or sub frequency mode.

4. Enters in STOP mode again.

5. Repeats 3 and 4.

When using STOP mode, if the watch timer interrupt inter-
val is selected to 2Hz, the power consumption can be
reduced considerably.

fW/211 (16Hz)

INTWT (16Hz)

500msec

WDTCL

500msec

If the WDTCL is not cleared
during this interval, the WDTOUTB
will be low during next interval.

The WDTCL should
be set during this interval.

fW/213 (4Hz)

fW/214 (2Hz)

INTWT (4Hz)

INTWT (2Hz)

WDT Reset
Signal

WDTOUTB

GMS81C5108

JUNE 2001 Ver 1.0

14. ANALOG TO DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has four analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation. The analog
supply voltage is connected to AV

of ladder resistance

of A/D module.

The A/D module has two registers which are the A/D mode
register (ADMR) and A/D data register (ADDR). The
ADMR register, shown in Figure 14-1, controls the opera-
tion of the A/D converter module. The port pins can be
configured as analog inputs or digital I/O. To use analog
inputs, each port should be assigned analog input port by

setting input mode by R2DR direction register. And select
the corresponding channel to be converted by setting
ADAN[1:0].

The processing of conversion is start when the start bit
ADST is set to "1". After one cycle, it is cleared by hard-
ware. The register ADDR contains the result of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADDR, the A/D conversion status bit
ADF is set to "1", and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
14-1. The A/D status bit ADF is automatically set when A/
D conversion is completed, cleared when A/D conversion
is in process. The conversion time takes maximum 30 uS
(at f

MAIN

= 4MHz).

Figure 14-1 A/D Converter Block Diagram & Registers

R20/AN0

R21/AN1

R22/AN2

R23/AN3

ANEN

S/H

Successive

Approximation

Circuit

A D IF

Resistor

Ladder

Circuit

ADAN[1:0]

ADDR (8-bit)

Sample & Hold

A/D Interrupt

ADDRESS : 0ED

RESET VALUE : Undefined

A/D Converter
Data Register

ANEN

ADMR (A/D Mode Register)

ADDRESS : 0EC

RESET VALUE : -0--0001

ADEN

ADAN1

ADAN0

ADST

ADF

ADF (A/D Status bit)
0 : A/D Conversion is in process
1 : A/D Conversion is completed

ADST (A/D Start bit)
1 : A/D Conversion is started
After 1 cycle, cleared to "0"
0 : Bit force to zero

00 : Channel 0 (R20/AN0)

01 : Channel 1 (R21/AN1)

10 : Channel 2 (R22/AN2)

11 : Channel 3 (R23/AN3)

ADEN (A/D Converter Enable bit)
1 : Enable
0 : Disable

ADDR (A/D Data Register)

ADDRESS : 0ED

RESET VALUE : Undefined

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

ADAN[1:0] (A/D Converter Input Selection)

Bit : 7 6 5 4 3 2 1 0

R/W

Bit : 7 6 5 4 3 2 1 0

Comparator

GMS81C5108

JUNE 2001 Ver 1.0

Figure 14-2 A/D Converter Operation Flow

A/D Converter Cautions

(1) Input range of AN0 to AN3

The input voltages of AN0 to AN3 should be within the
specification range. In particular, if a voltage above AV

or below V

is input (even if within the absolute maxi-

mum rating range), the conversion value for that channel
can not be indeterminated. The conversion values of the
other channels may also be affected.

(2) Noise countermeasures

In order to maintain 8-bit resolution, attention must be paid

to noise on pins AV

and AN0 to AN3. Since the effect

increases in proportion to the output impedance of the an-
alog input source, it is recommended that a capacitor is
connected externally as shown below in order to reduce
noise

Figure 14-3 Analog Input Pin Connecting Capacitor

(3) Pins AN0/R20 to AN3/R23

The analog input pins AN0 to AN3 also function as input/
output port (PORT R2) pins. When A/D conversion is per-
formed with any of pins AN0 to AN3 selected, be sure not
to execute a PORT input instruction while conversion is in
progress, as this may reduce the conversion resolution.

Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.

(4) AV

pin input impedance

A series resistor string of approximately 10K

is connect-

ed between the AV

pin and the V

pin.

Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the
series resistor string between the AV

pin and the V

pin, and there will be a large reference voltage error.

ENABLE A/D CONVERTER

A/D START (ADST = 1)

NOP

ADF = 1

A/D INPUT CHANNEL SELECT

READ ADDR

YES

ANALOG REFERENCE SELECT

AN0~AN3

100~1000pF

Analog
Input

GMS81C5108

JUNE 2001 Ver 1.0

15. Buzzer Output Function

The buzzer driver consists of 6-bit binary counter, the
buzzer data register BDR and the clock selector. It gener-
ates square-wave which is very wide range frequency (500
Hz~125 KHz at f

MAIN

= 4MHz) by user programmable

counter.

Pin R04 is assigned for output port of Buzzer driver by set-
ting the bit BUZ of Port Mode Register (PMR) to "1".

The 6-bit buzzer counter is cleared and start the counting
by writing signal to the register BDR. It is increased from
00

until it matches with BDR[5:0].

Also, it is cleared by counter overflow and count up to out-
put the square wave pulse of duty 50%.

The bit 0 to 5 of BDR determines output frequency for
buzzer driving. BCD is undefined after reset, so it must be
initialized to between 0

and 3F

by software. Note that

BDR is a write-only register. Frequency calculation is fol-
lowing as shown below.

The bits BCK1, BCK0 of BDR select the source clock
from prescaler output

BUZ

: BUZ pin frequency

Prescaler ratio: Prescaler divide ratio by BDR[7:6]
BCD value: 6-bit compare data, BCD[5:0].

Figure 15-1 Buzzer Driver

Example: 2.5kHz output at 4MHz.

LDM

R0DR,#XXX1_XXXXB

LDM

BDR,#1001_1000B

LDM

PMR,#XXX1_XXXXB ;Buzzer ON

X means don't care

BUZ

(

)

Oscillator Frequency

Prescaler Ratio

BCD

(

)

-------------------------------------------------------------------------------

BDR (Buzzer Data Register)

ADDRESS : 0FD

RESET VALUE : 00

BCK1

BCK0

BCD5

BCD4

BCD3

BCD2

BCD1

BCD0

MUX

COUNTER (6-bit)

BCD (6-bit)

F/F

COMPARATOR

BCK[1:0]

R04/BUZ PIN

BCK[1:0] (Buzzer Clock Source)

BCD[5:0] (Buzzer Control Data)

BUZ

[PMR.4]

Bit manipulation is not available.

Buzzer Period Data

Bit : 7 6 5 4 3 2 1 0

SCMR[1:0]

PMR (Port Mode Register)

ADDRESS :0D9

RESET VALUE : -0-00000

PWMO

BUZ

EC0

INT2

INT1

INT0

BUZ (Buzzer Output)
0: R04 Port (turn off buzzer)
1: BUZ port (turn on buzzer)

00: f

MAIN

01: f

MAIN

10: f

MAIN

11: f

MAIN

or f

SUB

or f

SUB

or f

SUB

or f

SUB

GMS81C5108

JUNE 2001 Ver 1.0

Buzzer Output Frequency

When main-frequency is 4MHz, buzzer frequency is
shown as below and if sub-frequency is selected as clock

source, buzzer frequency is used after dividing by 128.

Table 15-1 Buzzer Output Frequency

BDR

[5:0]

Frequency Output (kHz)

BDR

[5:0]

Frequency Output (kHz)

00
01
02
03
04
05
06
07

250.000
125.000

83.333
62.500
50.000
41.667
35.714
31.250

125.000

62.500
41.667
31.250
25.000
20.833
17.857
15.625

62.500
31.250
20.833
15.625
12.500
10.417

8.929
7.813

31.250
15.625
10.417

7.813
6.250
5.208
4.464
3.906

20
21
22
23
24
25
26
27

7.576
7.353
7.143
6.944
6.757
6.579
6.410
6.250

3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125

1.894
1.838
1.786
1.736
1.689
1.645
1.603
1.563

0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781

08
09

0A
0B
0C
0D
0E

27.778
25.000
22.727
20.833
19.231
17.857
16.667
15.625

13.889
12.500
11.364
10.417

9.615
8.929
8.333
7.813

6.944
6.250
5.682
5.208
4.808
4.464
4.167
3.906

3.472

3.125
2.841
2.604
2.404
2.232
2.083
1.953

28
29

2A
2B

2C
2D

6.098
5.952
5.814
5.682
5.556
5.435
5.319
5.208

3.049
2.976
2.907
2.841
2.778
2.717
2.660

2.604

1.524
1.488
1.453
1.420
1.389
1.359
1.330
1.302

0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651

10
11
12
13
14
15
16
17

14.706
13.889
13.158
12.500
11.905
11.364
10.870
10.417

7.353
6.944
6.579
6.250
5.952
5.682
5.435
5.208

3.676
3.472
3.289
3.125
2.976
2.841
2.717
2.604

1.838
1.736
1.645
1.563
1.488
1.420
1.359
1.302

30
31
32
33
34
35
36
37

5.102
5.000
4.902
4.808
4.717
4.630
4.545

4.464

2.551
2.500
2.451
2.404
2.358
2.315
2.273
2.232

1.276
1.250
1.225
1.202
1.179
1.157
1.136
1.116

0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558

18
19

1A
1B
1C
1D
1E

10.000

9.615
9.259
8.929
8.621
8.333
8.065
7.813

5.000
4.808
4.630
4.464
4.310
4.167
4.032
3.906

2.500
2.404
2.315
2.232
2.155
2.083
2.016
1.953

1.250
1.202
1.157
1.116
1.078
1.042
1.008
0.977

38
39

3A
3B

3C
3D

4.386
4.310
4.237
4.167
4.098
4.032
3.968
3.906

2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.953

1.096
1.078
1.059
1.042
1.025
1.008
0.992
0.977

0.548
0.539
0.530
0.521
0.512
0.504
0.496
0.488

GMS81C5108

JUNE 2001 Ver 1.0

16. Serial Communication Interface

The SCI module allows 8-bits of data to be synchronously
transmitted and received. This is useful for communication
with other peripheral of microcontroller devices.This con-

sists of serial I/O data register, serial I/O mode register,
clock selection circuit octal counter and control circuit as
shown in Figure 16-1.

Figure 16-1 SCI Registers and Block Diagram

SIOM (Seriol I/O Mode Register)

ADDRESS : 0FE

RESET VALUE : 00000001

POL

MSBS

SIO1

SIO0

SICK1

SICK0

SIOST

SIOSF

SIOD (Serial I/O Data Register)

ADDRESS : 0FF

RESET VALUE : Undefined

Bit : 7 6 5 4 3 2 1 0

R/W

POL (Polarity Selection)
0 : Data Transmission at falling edge
(Received data latch at rising edge)
1 : Data Transmission at rising edge
(Received data latch at falling edge)

SIO[1:0] (Serial I/O Operation Mode)
00 : Normal Port (R05, R06, R07)
01 : Transmit Mode (SCK, SO, R07)
10 : Receive Mode (SCK, R06, SI)
11 : Transmit & Receive Mode (SCK, SO, SI)

SIOST (Serial I/O Operation Start Control)
0 : SIO Operation Stop
1 : SIO Operation Start

(After one SCK clock become "0")

SICK[1:0] (Serial I/O Clock Source Selection)
00: f

MAIN

01: f

MAIN

10: T0O (Timer 0 Output)
11: External Clock

MSBS (MSB First Transmit and Receive Selection)
0 : LSB First
1 : MSB First

SIOSF (Serial I/O Status Flag)
0 : During SIO Operation
1 : SIO Operation Finished

Bit : 7 6 5 4 3 2 1 0

R/W

SIOD7

SIOD6

SIOD5

SIOD4

SIOD3

SIOD2

SIOD1

SIOD0

R06/SO

SCMR[1:0]

Pre-

scaler

SICK[1:0]

MAIN

or f

SUB

MAIN

or f

SUB

T0OV(Timer 0 Overflow)

R05

SCK

POL

SIO Control Circuit

SIOST

SIO[1:0] = 00

SICK[1:0]

& SIO[1:0]

MSBS

R07/SI

Octal Counter

SIO

(3-Bit)

SIOIF

Interrupt

SIOD(8-Bit)

SIO[1] = 1

MSBS

SIO[0] = 1

MSB

LSB

SCK

SIOSF

SIO Data Register

Start

Complete

Clock

Shift Clock

Clear

or f

SUB

or f

SUB

GMS81C5108

JUNE 2001 Ver 1.0

To accomplish communication, typically three pins are
used:

- Serial Data In

R07/SI

- Serial Data Out

R06/SO

- Serial Clock

R05/SCK

The serial data transfer operation mode is decided by set-

ting the SIO1 and SIO0 and the transfer clock rate is decid-
ed by setting the SICK1 and SICK0 of SCI Mode Control
Register as shown in Figure 16-1. And the polarity of
transfer clock is selected by setting the POL. The MSBS
bit is used to select which bit would be sending or receiv-
ing.

16.1 Data Transmit/Receive Timing

The SCI operation is executed by setting the SIOST bit to
"1". The SIOST bit is cleared to "0" automatically after 1
machine cycle. The Serial output data is shift in or shift out

at edge decided by POL. Interrupt is occurred when the
eight in/out datas is counted by octal counter.

Figure 16-2 SCI Timing Diagram

SIO1

SIO0

Function Selection

Port Selection

R05/SCK

R06/SO

R07/SI

R05

R06

R07

Transmit Mode

SCK

R07

Receive Mode

SCK

R06

Transmit and Receive

SCK

D 1

D 2

D 3

D 4

D 6

D 7

D 0

D 5

SIOST

R05/SCK

(POL=1)

R05/SCK

(POL=0)

R06/SO

R07/SI

SIOIF
(SCI Int. Req)

MSBS=0

SIOSF

GMS81C5108

JUNE 2001 Ver 1.0

17. INTERRUPTS

The GMS81C5108 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flag
(IRQH, IRQL), Interrupt Edge Selection Register (IESR),
priority circuit and Master enable flag ("I" flag of PSW).
The configuration of interrupt circuit is shown in Figure
17-1 and Interrupt priority is shown in Table 17-1 .

The flags that actually generate these interrupts are bit
INT0F, INT1F and INT2F in Register IRQH. When an ex-
ternal interrupt is generated, the flag that generated it is
cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.

The Timer 0 and Timer 2 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Basic Interval Timer Interrupt is generat-

ed by BITIF which is set by overflow of the Basic Interval
Timer Register (BITR).

Table 17-1 Interrupt Priority

Figure 17-1 Block Diagram of Interrupt Function

Reset/Interrupt

Symbol

Priority

Vector Addr.

Hardware Reset

Key Scan Interrupt

BIT Interrupt

External Interrupt 0
External Interrupt 1

Timer 0 Interrupt
Timer 1 Interrupt

External Interrupt 2

Remocon Interrupt

AD Interrupt

SIO Interrupt

Watch Timer Interrupt

RESET

BIT

INT0
INT1

T0
T1

INT2
REM

SIO

1
2
3
4
5
6
7
8
9

10
11

FFFE

FFFC

FFFA

FFF8

FFF6

FFF4

FFF2

FFF0

FFEE

FFEC

FFEA

FFE8

BIT

SIOIF

ADIF

A/D Converter

Remocon

Timer 1

Timer 0

Ext. Int. 1

Ext. Int. 0

IENH

Interrupt Enable

IRQH

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master
Enable Flag

I Flag

IENL

ior

i
t
y

ntr

I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.

KSIF

BITIF

INT0IF

INT1IF

REMIF

IESR

TOIF

T1IF

INT2IF

WTIF

Key Scan

Ext. Int. 2

SIO

GMS81C5108

JUNE 2001 Ver 1.0

The External Interrupts INT0, INT1 and INT2 can each be
transition-activated (1-to-0, 0-to-1 and both transiton).The
interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW), the interrupt enable register (IENH,
IENL) and the interrupt request flag (IRQH, IRQL) except
Power-on reset and software BRK interrupt.

Interrupt enable registers are shown in Figure 17-2. These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determine whether an interrupt
will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW

contains also a master enable bit, I-flag, which disables all
interrupts at once. When an interrupt is occurred, the I-flag
is cleared and disable any further interrupt, the return ad-
dress and PSW are pushed into the stack and the PC is vec-
tored to. Once in the interrupt service routine the source(s)
of the interrupt can be determined by polling the interrupt
request flag bits.

The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.

Figure 17-2 Interrupt Enable Registers and Interrupt Request Registers

17.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8 f

OSC

s at f

MAIN

=4MHz) after the completion of the current in-

struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
[RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

"0" to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to "0".

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address
is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

IENH (Interrupt Enable High Register)

ADDRESS : 0DB

RESET VALUE : -0000000

KSE

BITE

INT0E

INT1E

T0E

T1E

INT2E

ADDRESS : 0DA

RESET VALUE : -0000---

REME

ADE

SIOE

WTE

IENL (Interrupt Enable Low Register)

IRQH (Interrupt Request High Register)

IRQL (Interrupt Request Low Register)

0 : Disable
1 : Enable

Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.

0 : Not occurred
1 : Interrupt request is occurred

Shows the interrupt occurrence

Bit : 7 6 5 4 3 2 1 0

R/W

Bit : 7 6 5 4 3 2 1 0

R/W

ADDRESS : 0DD

RESET VALUE : -0000000

KSIF

BITIF

INT0IF

INT1IF

T0IF

T1IF

INT2IF

Bit : 7 6 5 4 3 2 1 0

R/W

ADDRESS : 0DC

RESET VALUE : -0000---

REMIF

ADIF

SIOIF

WTIF

Bit : 7 6 5 4 3 2 1 0

R/W

GMS81C5108

JUNE 2001 Ver 1.0

Figure 17-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

An interrupt request is not accepted until the I-flag is set to
"1" even if a requested interrupt has higher priority than
that of the current interrupt being serviced.

When nested interrupt service is required, the I-flag should
be set to "1" by "EI" instruction in the interrupt service
program. In this case, acceptable interrupt sources are se-
lectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. If necessary, these registers should be
saved by the software. Also, when multiple interrupt ser-
vices are nested, it is necessary to avoid using the same
data memory area for saving registers.

The following method is used to save/restore the general-
purpose registers.

Example: Register saving

General-purpose registers are saved or restored by using
push and pop instructions.

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Routine

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.

Basic Interval Timer

012

0E3

0FFFA

0FFFB

0E312

0E313

Entry Address

Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.

Vector Table Address

INTxx:

PUSH

;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.

interrupt processing

POP

RETI

;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN

main routine

interrupt
service routine

saving
registers

restoring
registers

acceptance of

interrupt

interrupt return

GMS81C5108

JUNE 2001 Ver 1.0

17.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.

Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in
Figure 17-4.

Figure 17-4 Execution of BRK/TCALL0

17.3 Multi Interrupt

If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.

However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.

Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.

TIMER1:

PUSH

LDM

IENH,#80H

;

Enable INT0 only

LDM

IENL,#0

;

Disable other

;

Enable Interrupt

:
:
:

:
:
:
LDM

IENH,#0FFH

;

Enable all interrupts

LDM

IENL,#0F0H

POP

RETI

Figure 17-5 Execution of Multi Interrupt

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

TCALL0

ROUTINE

RET

BRK or

TCALL0

enable INT0

TIMER 1
service

INT0
service

Main Program
service

Occur
TIMER1 interrupt

Occur
INT0

disable other

enable INT0
enable other

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

GMS81C5108

JUNE 2001 Ver 1.0

17.4 External Interrupt

The external interrupt on INT0, INT1 and INT2 pins are
edge triggered depending on the edge selection register
IESR (address 0D8

) as shown in Figure 17-6.

The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.

Figure 17-6 External Interrupt Block Diagram

Example: To use as an INT0 and INT2

:
:

;

**** Set port as an input port R0

LDM

R0DR,#1111_1010B

;

**** Set port as an interrupt port

LDM

PMR,#0000_0101B

;

**** Set Falling-edge Detection

LDM

IESR,#0001_0001B

:
:
:

Response Time

The INT0, INT1 and INT2 edge are latched into INT0F,
INT1F and INT2F at every machine cycle. The values are
not actually polled by the circuitry until the next machine
cycle. If a request is active and conditions are right for it to
be acknowledged, a hardware subroutine call to the re-
quested service routine will be the next instruction to be
executed. The DIV itself takes twelve cycles. Thus, a max-
imum of twelve complete machine cycles elapse between
activation of an external interrupt request and the begin-
ning of execution of the first instruction of the service rou-
tine.

Interrupt response timings are shown in Figure 17-7.

Figure 17-7 Interrupt Response Timing Diagram

INT0IF

INT0

INT0 INTERRUPT

INT1IF

INT1

INT1 INTERRUPT

INT2IF

INT2

INT2 INTERRUPT

IESR

[0D8

]

edge

sele

t
ion

IESR (Ext. Interrupt Edge Selection Register)

ADDRESS : 0D8

RESET VALUE : --000000

INT21

INT2[1:0] (INT2 Edge Selections)

Bit : 7 6 5 4 3 2 1 0

R/W

INT20

INT10

INT11

INT01

INT00

00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)

INT1[1:0] (INT1 Edge Selection)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)

INT0[1:0] (INT0 Edge Selections)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)

Interrupt Edge Selection Register)

Interrupt
goes
active

Interrupt
latched

Interrupt
processing

Interrupt
routine

8 f

OSC

max. 12 f

OSC

GMS81C5108

JUNE 2001 Ver 1.0

18. KEY SCAN

The key-scan block consists of key scan mode register
(KSMR) and R1 pull-up register (R1PU). When the key
scan interrupt is used, key scan mode register KSMR (ad-
dress 0F0

) should be set properly as shown in Figure 18-

1. The pins which is to be used as key scan input should be
set by KSMR and the strobe output pins should be set as
open drain. The strobe output pins could be selected from

among R0[7:0], R1[7:0], R2[3:0] and R3[3:0].

If the "L" signal is input to any one or more of key scan in-
put pins, the KSIF request flag is set to "1". This generates
an interrupt request. It also can be used in the way of re-
lease from STOP mode.

Figure 18-1 Key Scan Interrupt Block Diagram

Usage of Key Scan

When key board scanning, it is recommended that set the
output strobe to "L" first and then read R1 port after 60us

delay time. Because the rising time of the output strobe
port from "L" to "H" is so long. The Figure 18-2 explain
this reason.

Figure 18-2 Key Scan Timing

R13/KS3

R12/KS2

R11/KS1

R10/KS0

R1PU[7:0]

R17/KS7

R16/KS6

R15/KS5

R14/KS4

KSMR

KSIF

Key Scan
Interrupt

KSMR (Key Scan Mode Register)

ADDRESS : 0F0

RESET VALUE : 00

Bit : 7 6 5 4 3 2 1 0

R/W

KS7

KS6

KS5

KS4

KS3

KS2

KS1

KS0

0 : Port Function (I/O) Selection
1 : Key Scan Input Selection

R3<0>

R3<1>

R1 Port Read Timing

If the rising time is so long, the key scanning could be
detected double key with R3<0> and R3<1>.

;Program Example,

LDM
CALL
LDA

;R3<0> Port set to low
;60us time delay routine
;read R1 port

R3,#0000_1110b

Delay_60us

GMS81C5108

JUNE 2001 Ver 1.0

19. LCD DRIVER

The GMS81C5108 has the circuit that directly drives the
liquid crystal display (LCD) and its control circuit. The
Segment/Common Driver directly drives the LCD panel,
and the LCD Controller generates the segment/common
signals according to the RAM which stores display data. In
addition, VCL2 ~ VCL0 pin are provided as the drive pow-
er pins.

The GMS81C5108 has the following pins connected with
LCD.

Segment output port 37 pins (SEG0-SEG36)

2.Common output port 4 pins (COM0-COM3)

19.1 Configuration of LCD driver

Figure 19-1 shows the configuration of the LCD driver.

Figure 19-1 LCD Driver Block Diagram

COM0

SEG34/COM3

SEG35/COM2

SEG36/COM1

SEG0

spl

Data S

l
e

Control

l
a

y Da

ffe

i
s

t
e

LCD

Display Memory

egm

ent

/
C

on Driver

(37Nibbles)

128

256

ng Cont

r
o

SEG33

Select clock

clock

LCR[0F1H]

LCD

LCDEN

INT

RNAL

BUS

I
NE

MUX

WTMR[1:0]

M U X

SUB

MAIN

Prescal

MAIN

÷
÷
÷
÷

Select Duty

Control Register

GMS81C5108

JUNE 2001 Ver 1.0

19.2 Control of LCD Driver Circuit

The LCD driver is controlled by the LCD Control Register
(LCR). The LCR[1:0] determines the frequency of COM
signal scanning of each segment output. RESET clears the
LCD control register LCR values to logic zero. The LCD
display can continue to operate during SLEEP and STOP
modes if a sub-frequency clock is used as system clock
source. The constant voltage booster circuit for using LCD
driver is built in, so the definite voltage could supplied re-
gardless of power source voltage fluctuations.

Note: The Sub clock is used as voltage booster source
clock, so the stabilization time is need to use voltage boost-
er. Normally, the stabilization time is need more than
500ms. The external bias registers cannot be used for LCD
display supply voltage.

Figure 19-2 LCD Control Register

Selecting Frame Frequency

Frame frequency is set to the base frequency as shown in
the following Table 19-1. The f

is selected to f

SUB

(sub

clock) which is 32.768kHz.

The matters to be attended to use LCD driver

In reset state, LCD source clock is sub clock. So, when the
power is supplied, the LCD display would be flickered be-
fore the oscillation of sub clock is stabilized. It is recom-
mended to use LCD display on after the stabilization time
of sub clock is considered enough. If the LCD is reset dur-
ing display, the display would be blotted by the capacity of
LCD power circuit. The external circuit of constant voltage
booster for using LCD driver is shown at right.

Figure 19-3 LCD Power Booster Circuit

LCDEN (LCD Display Enable Bit)
0: LCD Display Disable
1: LCD Display Enable

VBCL (Voltage Booster Enable Bit)
0: Voltage Booster Disable
1: Voltage Booster Enable

LCDD[1:0] (LCD Duty Selection)
00: 1/4 Duty
01: 1/3 Duty (COM[3] are used as SEG[34])

LCR(LCD Control Register)

ADDRESS : 0F1

RESET VALUE : --000000

LCDEN

VBCL

LCDD1

LCDD0

LCK1

LCK0

Bit : 7 6 5 4 3 2 1 0

R/W

LCK (LCD Clock source selection)
00: f

01: f

10: f

128

11: f

256

The fs can be selected among f

SUB

(Sub clock), f

MAIN

(Main clck) and f

MAIN

(Main clock).

10: 1/2 Duty (COM[3:2] are used as SEG[34:35])
11: Static (COM[3:1] are used as SEG[34:36])

And sub or main is selected by WTCK[1:0] of WTMR.

LCR[1:0]

LCD clock

Frame Frequency (Hz)

Duty = Static

Duty = 1/2

Duty = 1/3

Duty = 1/4

00
01
10
11

128

256

1024

512
256
128

341.3
170.7

85.3
42.7

256
128

64
32

Table 19-1 Setting of LCD Frame Frequency

VCL2

VCL1

VCL0

GMS81C5108
GMS87C5108

CAPH

CAPL

C1~C4=0.47uF
R1=400K

R2=1M

GMS81C5108

JUNE 2001 Ver 1.0

19.3 LCD Display Memory

Display data are stored to the display data area (page 1) in
the data memory.
The display data stored to the display data area (address
0100

-0124

) are read automatically and sent to the LCD

driver by the hardware. The LCD driver generates the seg-
ment signals and common signals in accordance with the
display data and drive method. Therefore, display patterns
can be changed by only overwriting the contents of the dis-
play data area with a program. The table look up instruc-
tion is mainly used for this overwriting.
Figure 19.3 shows the correspondence between the display
data area and the SEG/COM pins. The LCD lights when
the display data is "1" and turn off when "0".

LCD display memory in this location that are not used for
LCD display can be allocated for general purpose use.

The SEG data for display is controlled by RPR (RAM Pag-
ing Register).

Figure 19-4 Setting of RAM Paging Register

Figure 19-5 LCD Display Memory

RPR (RAM Paging Register)

ADDRESS : 0F3

RESET VALUE : ------00

Bit : 7 6 5 4 3 2 1 0

R/W

RPR1

RPR0

RAM Page Instruction

RPR1

0 Page

CLRG

0 Page

SETG

1 Page

SETG

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

COM

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

Bit

0100

0101

0102

0103

0104

0105

0106

0107

0108

0109

010A

010B

010C

010D

010E

010F

0110

0111

0112

0113

0114

0115

0116

0117

0118

0119

011A

011B

011C

011D

011E

011F

0120

0121

0122

0123

0124

GMS81C5108

JUNE 2001 Ver 1.0

19.4 Control Method of LCD Driver

Initial Setting

Flow chart of initial setting is shown in Figure 19-6.

Example: Driving of LCD

Figure 19-6 Initial Setting of LCD Driver

Figure 19-7 Example of Connection COM & SEG

Display Data

Normally, display data are kept permanently in the pro-
gram memory and then stored at the display data area by
the table look-up instruction. This can be explained using
character display with 1/4 duty LCD as an example as well
as any LCD panel. The COM and SEG connections to the
LCD and display data are the same as those shown is Fig-
ure 19-7. Following is showing the Programming example
for displaying character.

Note: When power on RESET, sub oscillation start up time
is required. Enable LCD display after sub oscillation is sta-
bilized, or LCD may occur flicker at power on time shortly.

Clear

LCD Display

Memory

Select Frame Frequency

Turn on LCD

LDM

LCR,#12H

=64Hz, 1/4 duty

SUB

= 32.768kHz)

:
LDM

RPR,#1

;Select LCD Memory(1 page)

SETG

LDX

C_LCD1:

LDA

;RAM Clear
;(0100H->0124H)

STA

{X}+

CMPX

#025H

BNE

C_LCD1

CLRG
:
SET1

LCR.5

;Enable display

Setting of LCD drive method

Initialize of display memory

Enable display

SEG0

SEG1

COM3

COM0

COM1

COM2

Example: display "2"

100

101

bit 7

Note: * are don't care.

GMS81C5108

JUNE 2001 Ver 1.0

LCD Waveform

The LCD duty can be selected by LCR register. The kinds
of LCD waveforms are four totally. Among them, static

and 1/4 duty waveforms are shown Figure 19-8.

Figure 19-8 Example of LCD drive output

:
CLRG
LDX

#<DISPRAM

;Address included the data
;to be displayed.

GOLCD:

LDA

{X}

TAY
LDA

!FONT+Y

;LOAD FONT DATA

LDM

RPR,#1

;Set RPR = 1 to access LCD

SETG

;Set Page 1

LDX

STA

{X}+

;LOWER 4 BITS OF ACC. seg0

XCN
STA

{X}

;UPPER 4 BITS OF ACC. seg1

CLRG

;Set Page = 0

FONT

1101_0111B

; "0"

0000_0110B

; "1"

1110_0011B

; "2"

1010_0111B

; "3"

0011_0110B

; "4"

1011_0101B

; "5"

1111_0101B

; "6"

0000_0111B

; "7"

1111_0111B

; "8"

0011_0111B

; "9"

Font data

Write into the

LCD Memory

COM0

COM1

SEG0

SEG1 - COM0

SEG1

COM2

COM3

GND

VCL1
VCL0

1/4 Duty, 1/3 Bias Drive

SEG0 - COM0

VCL0

VCL1

VCL2

-VCL2

-VCL1

-VCL0

GND

VCL0

VCL1

VCL2

GND

VCL0

VCL1

VCL2

GND

VCL0

VCL1

VCL2

GND

VCL1
VCL0

VCL2

GND

VCL0

VCL1

VCL2

VCL0

VCL1

VCL2

-VCL2

-VCL1

-VCL0

VCL2

COM

SEG0

SEG1

SEG0

SEG1

COM3

COM0

COM1

COM2

GMS81C5108

JUNE 2001 Ver 1.0

20. REMOCON CARRIER GENERATOR

The GMS81C5108 has a circuit to generate carriers for the
remote controller. This circuit consists of Remocon Mode
Register (RMR), Carrier Frequency High Selection (CF-
HS), Carrier Frequency Low Selection (CFLS), Remocon
Data High Register (RDHR), Remocon Data Low Register
(RDLR), Remocon Data Counter (RDC), Remocon Output

Data Register (RODR) and Remocon Output Buffer
(ROB) as shown in Figure 20-1. A carrier duty and fre-
quency are determined by the contents of these registers. A
source clock input to the 6-bit counter is selected by diving
the frequency of the system clock by two (main or sub
clock).

20.1 Remocon Signal Output Control

The output of the REMOUT pin which outputs carriers is
controlled by RODR and ROB register. While the Bit-0 of
RODR is "1", the REMOUT pin outputs a carrier signal
generated by the remote controller carrier generator. While
this Bit is "0", the output of the REMOUT pin is low.

The content of the ROB is automatically transferred to the

RODR by an interrupt signal generated by the 8-Bit timer.
The content of the RODR.0 is output to the REMOUT pin.
Namely, the REMOUT pin outputs a high-level signal
when RODR.0 is "1" and a low-level signal when RODR.0
is "0".

Figure 20-1 Remocon Carrier Generator Block Diagram

SCMR[1:0]

Pre-

scaler

RDCK[2:0]

fxin

REN

& CCK[1:0]

Remocon

REMF

Interrupt

fxin

128

fxin

256

fxin

512

fxin

MUX

REN

6-Bit Counter

CFHS (6-Bit)

CFLS (6-Bit)

Comparator

RDC(8Bit)

RDHR (8-Bit)

RDLR (8-Bit)

Comparator

RDPE
REN

ROB (1Bit)

RODR (1Bit)

REMOUT

RMR (Remocon Mode Register)

ADDRESS : 0F6

RESET VALUE : -0000000

REN

CCK1

CCK0

RDPE

RDCK2

RDCK1

RDCK0

Bit : 7 6 5 4 3 2 1 0

R/W

REN (Remocon Operation Enable)
0 : Disable

RDCK[2:0] (Remocon Data Clock Selection)

CCK[1:0] (Carrier Clock Source Selection)

1 : Enable

RDPE (Remocon Data Pulse Enable)
0 : Disable
1 : Enable

111: Carrier Signal

fxin is f

MAIN

or f

SUB.

000: f

MAIN

001: f

MAIN

010: f

MAIN

011: f

MAIN

100: f

MAIN

101: f

MAIN

110: f

MAIN

: main-clock frequency

SUB

: sub-clock frequency

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

or f

SUB

00: f

MAIN

01: f

MAIN

10: f

MAIN

11: f

MAIN

or f

SUB

or f

SUB

or f

SUB

or f

SUB

GMS81C5108

JUNE 2001 Ver 1.0

Figure 20-2 Remocon Registers

20.2 Carrier Frequency

The carrier frequency and the pulse of data are calculated
by below formula. The the lengths of carrier frequency and
pulse of data are shown in Figure 20-3.

= source clock(RMR[5:4])

CFHS

= source clock(RMR[5:4])

CFHS

(Carrier Frequency) = 1/(t

)

= source clock(RMR[2:0])

RDHR

= source clock(RMR[2:0])

RDLR

CFHS (Carrier Frequency High Selection)

ADDRESS : 0F7

CFH5

CFH4

CFH3

CFH2

CFH1

CFH0

Bit : 7 6 5 4 3 2 1 0

RDHR (Remocon Data High Register)

ADDRESS : 0F9

RDH7

RDH6

RDH5

RDH4

RDH3

RDH2

RDH1

RDH0

Bit : 7 6 5 4 3 2 1 0

RESET VALUE : --111111

Carrier High Interval = The Value of CFHS x Clock Source Period

CFLS (Carrier Frequency Low Selection)

ADDRESS : 0F8

CFL5

CFL4

CFL3

CFL2

CFL1

CFL0

Bit : 7 6 5 4 3 2 1 0

RESET VALUE : --111111

Carrier Low Interval = The Value of CFLS x Clock Source Period

RESET VALUE : 11111111

Remocon Data High Interval = The Value of RDHR x Clock Source Period

RDLR (Remocon Data Low Register)

ADDRESS : 00FA

RDL7

RDL6

RDL5

RDL4

RDL3

RDL2

RDL1

RDL0

Bit : 7 6 5 4 3 2 1 0

RESET VALUE : 11111111

Remocon Data Low Interval = The Value of RDLR x Clock Source Period

RDC (Remocon Data Counter)

ADDRESS : 00FA

RDC7

RDC6

RDC5

RDC4

RDC3

RDC2

RDC1

RDC0

Bit : 7 6 5 4 3 2 1 0

RESET VALUE : 00000000

Remocon Data Counter Value

RODR (Remocon Output Data Register)

ADDRESS : 0FB

RDD0

Bit : 7 6 5 4 3 2 1 0

R/W

RESET VALUE : -------0

Remocon Data Output Value

ROB (Remocon Output Buffer)

ADDRESS : 0FC

RDB0

Bit : 7 6 5 4 3 2 1 0

R/W

RESET VALUE : -------0

Remocon Data Output Buffer

GMS81C5108

JUNE 2001 Ver 1.0

Figure 20-3 Carrier Frequency & Pulse of Data

The Table 20-1 shows high and low length of carrier fre-
quency according to CFLS and CFHS. This only shows

when the source clock is selected f

MAIN

and f

MAIN

÷2

4MHz.

Table 20-1 Length of Carrier Frequency (at 4MHz)

ROD0 = 01

ROD0 = 00

As soon as the carrier interrupt is occurred,
the content of ROB is transferred to RODR.

Carrier Frequency

Pulse of Data

Set Value

Selection of PS0

Selection of PS2

Set Value

Selection of PS0

Selection of PS2

CFHS

CFLS

(us)

CFHS

CFLS

(us)

03H

0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
6.25
6.50
6.75
7.00
7.25
7.50
7.75

1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00

10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
19.00
20.00
21.00
22.00
23.00
24.00
25.00
26.00
27.00
28.00
29.00
30.00
31.00

1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00

10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
19.00
20.00
21.00
22.00
23.00
24.00
25.00
26.00
27.00
28.00
29.00
30.00
31.00

8.00
8.25
8.50
8.75
9.00
9.25
9.50
9.75

10.00
10.25
10.50
10.75
11.00
11.25
11.50
11.75
12.00
12.25
12.50
12.75
13.00
13.25
13.50
13.75
14.00
14.25
14.50
14.75
15.00
15.25
15.50
15.75

8.00
8.25
8.50
8.75
9.00
9.25
9.50
9.75

10.00
10.25
10.50
10.75
11.00
11.25
11.50
11.75
12.00
12.25
12.50
12.75
13.00
13.25
13.50
13.75
14.00
14.25
14.50
14.75
15.00
15.25
15.50
15.75

32.00
33.00
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
42.00
43.00
44.00
45.00
46.00
47.00
48.00
49.00
50.00
51.00
52.00
53.00
54.00
55.00
56.00
57.00
58.00
59.00
60.00
61.00
62.00
63.00

GMS81C5108

JUNE 2001 Ver 1.0

Example:

Carrier Frequency = 37.8kHz, high = 8.52ms, low = 4.24ms, @4MHz

Rem_sig: LDM

RMR,#0001_0010B ;carrier clock(PS1), remocon data clock(PS5)

LDM

CFHS,#18

;carrier low(IR LED)=18*PS1(0.5us)=9us

LDM

CFLS,#35

;carrier high(IR LED)=35*PS1(0.5us)=17.5us

CLR1

ROD0

LDM

R_bit,#1111_1000B

LDM

RDHR,#213

;213*5*PS5(8us)=8.52ms

LDM

RDLR,#177

;177*3*PS5(8us)=4.248ms

LDX

CALL

DATA

SET1

RMR.6

;Remocon operation enable

SET1

RMR.3

;Remocon data pulse enable

SET1

IENL.6

;Remocon int.

Loop1:

NOP
CMPX

BNE

Loop1

Finish:

CLR1

ROD0

CLR1

ROB0

RET

;********
Data:

ROL

R_bit

BCS

Set_rob0

CLR1

ROB0

RET

Set_rob0:SET1ROB0

RET

;***********************************************;
; Remocon int service routine ;
;***********************************************;
;
Remocon_INT:

CALL

Data

DEC

RETI

GMS81C5108

JUNE 2001 Ver 1.0

21. OSCILLATOR CIRCUIT

The GMS81C5108 has two oscillation circuits internally.
X

and X

OUT

are input and output for main frequency and

and SX

OUT

are input and output for sub frequency,

respectively, inverting amplifier which can be configured
for being used as an on-chip oscillator, as shown in Figure
21-1.

Figure 21-1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.

In addition, see Figure 21-2 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wir-
ing to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
V

. Do not ground it to any ground pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Figure 21-2 Layout of Oscillator PCB circuit

OUT

Recommend

C1,C2 = 20pF

OUT

External Clock

Open

OUT

External Oscillator

RC Oscillator

Crystal or Ceramic Oscillator

OUT

Recommend
C3,C4 = 30pF

32.768KHz

4.19MHz

Crystal Oscillator

Ceramic Resonator

C1,C2 = 20pF

Select R value according to AC Characteristics.

EXT

The Cap. is built in(5pF).

OUT

GMS81C5108

JUNE 2001 Ver 1.0

22. RESET

The GMS81C5108 have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-

dog timer reset. Table 22-1 shows on-chip hardware ini-
tialization by reset action.

Table 22-1 Initializing Internal Status by Reset Action

22.1 External Reset Input

The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin to low for at least 8 oscillator periods, within
the operating voltage range and oscillation stable, it is ap-
plied, and the internal state is initialized. After reset,
65.5ms (at 4MHz) add with 7 oscillator periods are re-
quired to start execution as shown in Figure 22-2.

Internal RAM is not affected by reset. When V

is turned

on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.

When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at FFFE

- FFFF

A connection for simple power-on-reset is shown in Figure
22-1.

Figure 22-1 Simple Power-on-Reset Circuit

Figure 22-2 Timing Diagram after RESET

22.2 Watchdog Timer Reset

Refer to "13.2 Watch Dog Timer" on page 57.

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(PC)

(FFFF

) - (FFFE

)

Peripheral clock

RAM page register

(RPR)

SVD

Enable

G-flag

(G)

Control registers

Refer to Table 8-1 on page 25

Operation mode

Main-frequency clock

Voltage Booster

Disable

RESET

GND

Mask Option

MCU

100k

1uF

MAIN PROGRAM

System Clock

FFFE FFFF

Stabilization Time

= 65.5mS at 4MHz

RESET

ADDRESS

DATA

Start

ADL

ADH

BUS

RESET Process Step

x 256

MAIN

1024

GMS81C5108

JUNE 2001 Ver 1.0

23. SUPPLY VOLTAGE DETECTION

The GMS81C5108 has an on-chip low voltage detection
circuitry to detect the V

voltage. A configuration regis-

ter, SCMR, can enable or disable the low voltage detect
circuitry. This GMS81C5108 has two level detec-
tor(SVD0, SVD1). The SVD0 flag is set when the V

falls below 2.2V and if the V

is rise above 2.2V the

SVD0 is cleared automatically. The SVD1 flag is set when
the V

falls below 1.7V and if this flag is set once, it is

not cleared automatically although the V

rises above

1.7V. It can be cleared by writing.

If the SVD1 is set, the MCU can be RESET or frozen by
the flag SVRT. In the in-circuit emulator, supply voltage
detection is not implemented and user can not experiment
with it. Therefore, after final development of user program,
this function may be experimented or evaluated.

Figure 23-1 Low Voltage Detector Register

Figure 23-2 Power Fail Processor Situations

* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.

R/W

SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)

SCS[1:0] (System clock source select)

INITIAL VALUE: 00

ADDRESS: 0F5

SCMR (System

MSB

LSB

R/W

SVD[1:0] (SVD Flag)
SVD0 : set at VDD=2.2V
SVD1 : set at VDD=1.7V

SVRT (System Reset Control by SVD1 Bit)
0 : System reset by SVD1 Flag
1 : Don't system reset by SVD1 Flag (Freeze)

SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable

Clock Mode Register)

MAIN

or f

SUB

or f

SUB

or f

SUB

or f

SUB

Internal
RESET

SVD

MAX

SVD MIN

SVD MAX
SVD MIN

65.5mS

t < 65.5mS

65.5mS

When SVRT = 0

SVD MAX
SVD MIN

When SVRT = 1

System

Clock

System

Clock

GMS81C5108

JUNE 2001 Ver 1.0

24. DEVEMOPMENT TOOLS

24.1 OTP Programming

The GMS87C5108 is an OTP (One Time Programmable) micro-
controllers. Its internal user memory is constructed with EPROM
(Electrically Programmable Read Only Memory).

The OTP microcontroller is generally used for chip evaluation,
first production, small amount production, fast mass production,
etc.

Blank OTP's internal EPROM is filled by 00

, not FF

Note: In any case, you have to use the *.OTP file for pro-
gramming, not the *.HEX file. After assemble, both OTP
and HEX file are generated by automatically. The HEX file
is used during program emulation on the emulator.

How to Program

To program the OTP devices, user can use Hynix own program-
mer.

Hynix

own programmer list

Manufacturer: Hynix Semiconductor Programmer:

Choice-Sigma
Choice-Gang4

The Choice-Sigma is a Hynix Universal Single Programmer for
all of Hynix OTP devices, also the Choice-Gang4 can program
four OTPs at once for Hynix OTP.

Ask to Hynix sales part for purchasing or more detail

Programming Procedure

1. Select device

GMS87C5108

you want.

2. Load the *.OTP file from the PC. The file is composed

of Motorola-S1 format.

3. Set the programming address range as below table.

4. Mount the socket adapter on the programmer.

5. Start program/verify.

Pin Function

(Program Voltage)

is the input for the program voltage for programming the

EPROM.

CE (Chip Enable)
CE is the input for programming and verifying internal EPROM.

OE (Output Enable)
OE is the input of data output control signal for verify.

A0~A15 (Address Bus)
A0~A15 are address input pins for internal EPROM.

O0~O7 (EPROM Data Bus)
These are data bus for internal EPROM.

Address

Set Value

Buffer start address

E000

Buffer end address

FFFF

Device start address

E000

S81C51

NE 2001

Ver

1.0

.2 Emulat

or S/W Sett

ing

POWER

RUN

STOP

SLEEP

CHO

ICE-

r
.
EV

A 81C51

B/D Rev 1.0

/
N

.
-

-
-
-
-
---

CONNECTA

CONNECTB

CONNECTC

J_USERB

RESET

J_USERA

V_USER

X1 (OSC)

/RESET

XOUT

VLC

SEG46

SEG44

SEG42

SEG40

SEG38

VREG

COM1/S36

COM3/S34

SEG32

SEG30

SEG28

SEG26

SEG24

SEG22

SEG20

SEG18

SEG16

SEG14

SEG12

SEG10

SEG8

SEG6

SEG4

SEG2

SEG0

SEG47

SEG45

SEG43

SEG41

SEG39

SEG37

COM0

COM2/S35

SEG33

SEG31

SEG29

SEG27

SEG25

SEG23

SEG21

SEG19

SEG17

SEG15

SEG13

SEG11

SEG9

SEG7

SEG5

SEG3

SEG1

GND

VCL1

VLCDC

GND

REMOUT (TONED)

GND

R36

R34

R21

R23

R25

R27

R16

R14

R12

R10

R06

R04

R02

R00

R32

R30

+5V

GND

VCL0

VCL2

GND

/U_RST

U_XOUT

GND

R37

R35

R20

R22

R24

R26

R17

R15

R13

R11

R07

R05

R03

R01

R33

R31

+5V

J_USERB

J_USERA

l
O

illa

t
o

Socket

EVA

2 1

OFF ON

FF O

VR1

VR2

GMS81C5108

JUNE 2001 Ver 1.0

DIP Switch and VR Setting

Before execute the user program, keep in your mind the below configuration

DIP S/W, VR

Description

ON/OFF Setting

SW1

Emulator Reset Switch. Reset the Emulator.

Reset the Emulator.

SW2

Normally OFF.
EVA. chip can be reset by external
user target system board.
ON : Reset is available by user
target system board.
OFF : MCU is reset by REST switch
on EVA. board.

Normally OFF.
MCU XOUT pin are disconnected
by Emulator internally. Some cir-
cumstance user may connect this
circuit.
ON : Output XOUT signal
OFF : Disconnect circuit

SW4

1
2
3

Normally ON.
It serves the external bias resistors.
If user want to use external circuit
instead of internal R, turn on these
switches.

4
5
6

LCD Voltage booster circuit.

Must be ON position.
It is used for the GMS81C5108.

Select the Stack Page.

Must be OFF position.
This switch decide the Stack page 0
(off) or page 1 (on).
ON : For the GMS81C7XXX
OFF : For the GMS81C5108

GMS81C5108 detect the V

voltage but Emulator can not do

because Emulator can not operate if V

is below normal opr.

voltage (5V), This switch serves LVD environment through the
applying 0V to LVD pin of EVA. chip during 5V normal operation.

Position ON during normal opera-
tion.
ON : Normal operation
OFF : Force to detect the LVD, refer
to "23. SUPPLY VOLTAGE DETEC-
TION" on page 82.

SW2-1

RESET pin

EVA.
Chip

SW2-2

XOUT pin

EVA.
Chip

Oscillator

VCL1

VCL2

External Resistor

VCL0

Adjust Contrast

SW4-1

SW4-2

SW4-3

0.47uF

10k

and Capacitor

VR1 50k

SW4-8

EVA.
Chip

LVD pin

OFF ON

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

A. CONTROL REGISTER LIST

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

00C0

R0 port data register

R/W

0 0 0 0 0 0 0 0

00C1

R1 port data register

R/W

0 0 0 0 0 0 0 0

00C2

R2 port data register

R/W

- - - - 0 0 0 0

00C3

R3 port data register

R/W

- - - - 0 0 0 0

00C8

R0 port I/O direction register

R0DR

0 0 0 0 0 0 0 0

00C9

R1 port I/O direction register

R1DR

0 0 0 0 0 0 0 0

00CA

R2 port I/O direction register

R2DR

- - - - 0 0 0 0

00CB

R3 port I/O direction register

R3DR

- - - - 0 0 0 0

00D0

R0 port pull-up register

R0PU

0 0 0 0 0 0 0 0

00D1

R1 port pull-up register

R1PU

0 0 0 0 0 0 0 0

00D2

R2 port pull-up register

R2PU

- - - - 0 0 0 0

00D3

R3 port pull-up register

R3PU

- - - - 0 0 0 0

00D4

R0 port open drain control register

R0CR

0 0 0 0 0 0 0 0

00D5

R1 port open drain control register

R1CR

0 0 0 0 0 0 0 0

00D6

R2 port open drain control register

R2CR

- - - - 0 0 0 0

00D7

R3 port open drain control register

R3CR

- - - - 0 0 0 0

00D8

Ext. interrupt edge selection register

IESR

R/W

- - 0 0 0 0 0 0

00D9

Port selection register

PMR

R/W

- 0 - 0 0 0 0 0

00DA

Interrupt enable low register

IENL

R/W

- 0 0 0 0 - - -

00DB

Interrupt enable high register

IENH

R/W

- 0 0 0 0 0 0 0

00DC

Interrupt request flag low register

IRQL

R/W

- 0 0 0 0 - - -

00DD

Interrupt request flag high register

IRQH

R/W

- 0 0 0 0 0 0 0

00DE

Sleep mode register

SMR

R/W

- - - - - - - 0

00E0

Timer 0 mode register

TM0

R/W

- - 0 0 0 0 0 0

00E1

Timer 0 counter register

0 0 0 0 0 0 0 0

Timer 0 data register

TDR0

1 1 1 1 1 1 1 1

Timer 0 input capture register

CDR0

0 0 0 0 0 0 0 0

00E2

Timer 1 mode register

TM1

R/W

0 0 0 0 0 0 0 0

00E3

Timer 1 data register

TDR1

1 1 1 1 1 1 1 1

PWM0 pulse period register

T1PPR

1 1 1 1 1 1 1 1

00E4

Timer 1 counter register

0 0 0 0 0 0 0 0

Timer 1 input capture register

CDR1

0 0 0 0 0 0 0 0

PWM0 pulse duty register

T1PDR

R/W

0 0 0 0 0 0 0 0

00E5

PWM0 high register

PWMHR

- - - - 0 0 0 0

00EC

A/D converter mode register

ADMR

R/W

- 0 - - 0 0 0 1

00ED

A/D converter data register

ADDR

x x x x x x x x

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

00EF

Watch timer mode register

WTMR

R/W

- 0 0 0 0 0 0 0

00F0

Key scan mode register

KSMR

R/W

0 0 0 0 0 0 0 0

00F1

LCD control register

LCR

R/W

0 0 0 0 0 0 0 0

00F3

RAM paging register

RPR

R/W

- - - - - - 0 0

00F4

Basic interval timer register

BITR

0 0 0 0 0 0 0 0

Clock control register

CKCTLR

- - - - 0 1 1 1

00F5

System clock mode register

SCMR

R/W

0 0 0 0 0 0 0 0

00F6

Remocon mode register

RMR

R/W

- 0 0 0 0 0 0 0

00F7

Carrier frequency high selection

CFHS

- - 1 1 1 1 1 1

00F8

Carrier frequency low selection

CFLS

- - 1 1 1 1 1 1

00F9

Remocon data high register

RDHR

1 1 1 1 1 1 1 1

00FA

Remocon data low register

RDLR

1 1 1 1 1 1 1 1

Remocon data counter

RDC

0 0 0 0 0 0 0 0

00FB

Remocon output data register

RODR

R/W

- - - - - - - 0

00FC

Remocon output buffer

ROB

R/W

- - - - - - - 0

00FD

Buzzer data register

BDR

0 0 0 0 0 0 0 0

00FE

Serial I/O mode register

SIOM

R/W

0 0 0 0 0 0 0 1

00FF

Serial I/O data register

SIOD

R/W

x x x x x x x x

Address

Register Name

Symbol

R/W

Initial Value

Page

7 6 5 4 3 2 1 0

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

iii

B. INSTRUCTION

B.1 Terminology List

Terminology

Description

Accumulator

X - register

Y - register

PSW

Program Status Word

#imm

8-bit Immediate data

Direct Page Offset Address

!abs

Absolute Address

[ ]

Indirect expression

{ }

{ }+

.bit

Bit Position

A.bit

Bit Position of Accumulator

dp.bit

Bit Position of Direct Page Memory

M.bit

Bit Position of Memory Data (000

~0FFF

)

rel

Relative Addressing Data

upage

U-page (0FF00

~0FFFF

) Offset Address

Table CALL Number (0~15)

Addition

Upper Nibble Expression in Opcode

Subtraction

Multiplication

Division

( )

Contents Expression

AND

Exclusive OR

NOT

Assignment / Transfer / Shift Left

Shift Right

Exchange

Equal

Not Equal

Bit Position

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

B.2 Instruction Map

LOW

HIGH

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

000

SET1
dp.bit

BBS

A.bit,rel

BBS

dp.bit,rel

ADC

#imm

ADC

dp+X

ADC

!abs

ASL

TCALL

SETA1

.bit

BIT

POP

PUSH

BRK

001

CLRC

SBC

#imm

SBC

dp+X

SBC

!abs

ROL

TCALL

CLRA1

.bit

COM

POP

PUSH

BRA

rel

010

CLRG

CMP

#imm

CMP

dp+X

CMP

!abs

LSR

TCALL

NOT1

M.bit

TST

POP

PUSH

PCALL

Upage

011

#imm

dp+X

!abs

ROR

TCALL

OR1

OR1B

CMPX

POP

PSW

PUSH

PSW

RET

100

CLRV

AND

#imm

AND

dp+X

AND

!abs

INC

TCALL

AND1

AND1B

CMPY

CBNE

dp+X

TXSP

INC

101

SETC

EOR

#imm

EOR

dp+X

EOR

!abs

DEC

TCALL

EOR1

EOR1B

DBNE

XMA

dp+X

TSPX

DEC

110

SETG

LDA

#imm

LDA

dp+X

LDA
!abs

TXA

LDY

TCALL

LDC

LDCB

LDX

dp+Y

XCN

DAS

111

LDM

dp,#imm

STA

dp+X

STA
!abs

TAX

STY

TCALL

STC

M.bit

STX

dp+Y

XAX

STOP

LOW

HIGH

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

000

BPL

rel

CLR1

dp.bit

BBC

A.bit,rel

BBC

dp.bit,rel

ADC

{X}

ADC

!abs+Y

ADC

[dp+X]

ADC

[dp]+Y

ASL
!abs

ASL

dp+X

TCALL

JMP

!abs

BIT

!abs

ADDW

LDX

#imm

JMP

[!abs]

001

BVC

rel

SBC

{X}

SBC

!abs+Y

SBC

[dp+X]

SBC

[dp]+Y

ROL

!abs

ROL

dp+X

TCALL

CALL

!abs

TEST

!abs

SUBW

LDY

#imm

JMP

[dp]

010

BCC

rel

CMP

{X}

CMP

!abs+Y

CMP

[dp+X]

CMP

[dp]+Y

LSR
!abs

LSR

dp+X

TCALL

MUL

TCLR1

!abs

CMPW

CMPX

#imm

CALL

[dp]

011

BNE

rel

{X}

!abs+Y

[dp+X]

[dp]+Y

ROR

!abs

ROR

dp+X

TCALL

DBNE

CMPX

!abs

LDYA

CMPY

#imm

RETI

100

BMI

rel

AND

{X}

AND

!abs+Y

AND

[dp+X]

AND

[dp]+Y

INC

!abs

INC

dp+X

TCALL

DIV

CMPY

!abs

INCW

INC

TAY

101

BVS

rel

EOR

{X}

EOR

!abs+Y

EOR

[dp+X]

EOR

[dp]+Y

DEC

!abs

DEC

dp+X

TCALL

XMA

{X}

XMA

DECW

DEC

TYA

110

BCS

rel

LDA

{X}

LDA

!abs+Y

LDA

[dp+X]

LDA

[dp]+Y

LDY
!abs

LDY

dp+X

TCALL

LDA
{X}+

LDX
!abs

STYA

XAY

DAA

111

BEQ

rel

STA

{X}

STA

!abs+Y

STA

[dp+X]

STA

[dp]+Y

STY
!abs

STY

dp+X

TCALL

STA
{X}+

STX
!abs

CBNE

XYX

NOP

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

B.3 Instruction Set

Arithmetic / Logic Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADC #imm

Add with carry.

ADC dp

( A ) + ( M ) + C

ADC dp + X

ADC !abs

NV--H-ZC

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

AND #imm

Logical AND

AND dp

( A )

( M )

AND dp + X

AND !abs

N-----Z-

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

Arithmetic shift left

ASL dp

N-----ZC

ASL dp + X

ASL !abs

CMP #imm

Compare accumulator contents with memory contents
( A ) - ( M )

CMP dp

CMP dp + X

CMP !abs

N-----ZC

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

Compare X contents with memory contents

CMPX dp

( X ) - ( M )

N-----ZC

CMPX !abs

CMPY #imm

Compare Y contents with memory contents

CMPY dp

( Y ) - ( M )

N-----ZC

CMPY !abs

COM dp

1'S Complement : ( dp )

~( dp )

N-----Z-

DAA

Decimal adjust for addition

N-----ZC

DAS

Decimal adjust for subtraction

N-----ZC

DEC A

Decrement

N-----Z-

DEC dp

( M ) - 1

N-----Z-

DEC dp + X

N-----Z-

DEC !abs

N-----Z-

DEC X

N-----Z-

DEC Y

N-----Z-

7 6 5 4 3 2 1 0

"0"

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

DIV

Divide : YA / X Q: A, R: Y

NV--H-Z-

EOR #imm

Exclusive OR

EOR dp

( A )

( M )

EOR dp + X

EOR !abs

N-----Z-

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

Increment

N-----ZC

INC dp

( M ) + 1

N-----Z-

INC dp + X

N-----Z-

INC !abs

N-----Z-

INC X

N-----Z-

INC Y

N-----Z-

LSR A

Logical shift right

LSR dp

N-----ZC

LSR dp + X

LSR !abs

MUL

Multiply : YA

N-----Z-

OR #imm

Logical OR

OR dp

( A )

( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through Carry

ROL dp

N-----ZC

ROL dp + X

ROL !abs

ROR A

Rotate right through Carry

ROR dp

N-----ZC

ROR dp + X

ROR !abs

SBC #imm

Subtract with Carry

SBC dp

( A ) - ( M ) - ~( C )

SBC dp + X

SBC !abs

NV--HZC

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

TST dp

Test memory contents for negative or zero, ( dp ) - 00

N-----Z-

XCN

Exchange nibbles within the accumulator
A

N-----Z-

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

7 6 5 4 3 2 1 0

"0"

7 6 5 4 3 2 1 0

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

vii

Register / Memory Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

LDA #imm

Load accumulator

LDA dp

( M )

LDA dp + X

LDA !abs

LDA !abs + Y

N-----Z-

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

X- register auto-increment : A

( M ) , X

X + 1

LDM dp,#imm

Load memory with immediate data : ( M )

imm

--------

LDX #imm

Load X-register

LDX dp

( M )

N-----Z-

LDX dp + Y

LDX !abs

LDY #imm

Load Y-register

LDY dp

( M )

N-----Z-

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

( M )

STA !abs

STA !abs + Y

--------

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

X- register auto-increment : ( M )

A, X

X + 1

STX dp

Store X-register contents in memory

STX dp + Y

( M )

--------

STX !abs

STY dp

Store Y-register contents in memory

STY dp + X

( M )

--------

STY !abs

TAX

Transfer accumulator contents to X-register : X

N-----Z-

TAY

Transfer accumulator contents to Y-register : Y

N-----Z-

TSPX

Transfer stack-pointer contents to X-register : X

N-----Z-

TXA

Transfer X-register contents to accumulator: A

N-----Z-

TXSP

Transfer X-register contents to stack-pointer: sp

N-----Z-

TYA

Transfer Y-register contents to accumulator: A

N-----Z-

XAX

Exchange X-register contents with accumulator :X

--------

XAY

Exchange Y-register contents with accumulator :Y

--------

XMA dp

Exchange memory contents with accumulator

XMA dp+X

( M )

N-----Z-

XMA {X}

XYX

Exchange X-register contents with Y-register : X

--------

GMS81C5108 APPENDIX

viii

JUNE 2001 Ver 1.0

16-BIT operation

Bit Manipulation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

ADDW dp

16-Bits add without Carry
YA

( YA ) + ( dp +1 ) ( dp )

NV--H-ZC

CMPW dp

Compare YA contents with memory pair contents :
(YA)

(dp+1)(dp)

N-----ZC

DECW dp

Decrement memory pair
( dp+1)( dp)

( dp+1) ( dp) - 1

N-----Z-

INCW dp

Increment memory pair
( dp+1) ( dp)

( dp+1) ( dp ) + 1

N-----Z-

LDYA dp

Load YA
YA

( dp +1 ) ( dp )

N-----Z-

STYA dp

Store YA
( dp +1 ) ( dp )

--------

SUBW dp

16-Bits subtract without carry
YA

( YA ) - ( dp +1) ( dp)

NV--H-ZC

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

AND1 M.bit

Bit AND C-flag : C

( C )

( M .bit )

-------C

AND1B M.bit

Bit AND C-flag and NOT : C

( C )

~( M .bit )

-------C

BIT dp

Bit test A with memory :

MM----Z-

BIT !abs

( A )

( M ) , N

( M

) , V

( M

)

CLR1 dp.bit

Clear bit : ( M.bit )

"0"

--------

CLRA1 A.bit

Clear A bit : ( A.bit )

"0"

--------

CLRC

Clear C-flag : C

"0"

-------0

CLRG

Clear G-flag : G

"0"

--0-----

CLRV

Clear V-flag : V

"0"

-0--0---

EOR1 M.bit

Bit exclusive-OR C-flag : C

( C )

( M .bit )

-------C

EOR1B M.bit

Bit exclusive-OR C-flag and NOT : C

( C )

~(M .bit)

-------C

LDC M.bit

Load C-flag : C

( M .bit )

-------C

LDCB M.bit

Load C-flag with NOT : C

~( M .bit )

-------C

NOT1 M.bit

Bit complement : ( M .bit )

~( M .bit )

--------

OR1 M.bit

Bit OR C-flag : C

( C )

( M .bit )

-------C

OR1B M.bit

Bit OR C-flag and NOT : C

( C )

~( M .bit )

-------C

SET1 dp.bit

Set bit : ( M.bit )

"1"

--------

SETA1 A.bit

Set A bit : ( A.bit )

"1"

--------

SETC

Set C-flag : C

"1"

-------1

SETG

Set G-flag : G

"1"

--1-----

STC M.bit

Store C-flag : ( M .bit )

--------

TCLR1 !abs

Test and clear bits with A :
A - ( M ) , ( M )

( M )

~( A )

N-----Z-

TSET1 !abs

Test and set bits with A :
A - ( M ) , ( M )

( M )

( A )

N-----Z-

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

Branch / Jump Operation

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BBC A.bit,rel

4/6

Branch if bit clear :

--------

BBC dp.bit,rel

5/7

if ( bit ) = 0 , then pc

( pc ) + rel

BBS A.bit,rel

4/6

Branch if bit set :

--------

BBS dp.bit,rel

5/7

if ( bit ) = 1 , then pc

( pc ) + rel

BCC rel

2/4

Branch if carry bit clear
if ( C ) = 0 , then pc

( pc ) + rel

--------

BCS rel

2/4

Branch if carry bit set
if ( C ) = 1 , then pc

( pc ) + rel

--------

BEQ rel

2/4

Branch if equal
if ( Z ) = 1 , then pc

( pc ) + rel

--------

BMI rel

2/4

Branch if minus
if ( N ) = 1 , then pc

( pc ) + rel

--------

BNE rel

2/4

Branch if not equal
if ( Z ) = 0 , then pc

( pc ) + rel

--------

BPL rel

2/4

Branch if minus
if ( N ) = 0 , then pc

( pc ) + rel

--------

BRA rel

Branch always
pc

( pc ) + rel

--------

BVC rel

2/4

Branch if overflow bit clear
if (V) = 0 , then pc

( pc) + rel

--------

BVS rel

2/4

Branch if overflow bit set
if (V) = 1 , then pc

( pc ) + rel

--------

CALL !abs

Subroutine call

CALL [dp]

M( sp)

( pc

), sp

sp - 1, M(sp)

(pc

), sp

sp - 1,

if !abs, pc

abs ; if [dp], pc

( dp ), pc

( dp+1 ) .

--------

CBNE dp,rel

5/7

Compare and branch if not equal :

--------

CBNE dp+X,rel

6/8

if ( A )

( M ) , then pc

( pc ) + rel.

DBNE dp,rel

5/7

Decrement and branch if not equal :

--------

DBNE Y,rel

4/6

if ( M )

0 , then pc

( pc ) + rel.

JMP !abs

Unconditional jump

JMP [!abs]

jump address

--------

JMP [dp]

PCALL upage

U-page call
M(sp)

( pc

), sp

sp - 1, M(sp)

( pc

sp - 1, pc

( upage ), pc

"0FF

" .

--------

TCALL n

Table call : (sp)

( pc

), sp

sp - 1,

M(sp)

( pc

),sp

sp - 1,

(Table vector L), pc

(Table vector H)

--------

GMS81C5108 APPENDIX

JUNE 2001 Ver 1.0

Control Operation & Etc.

No.

Mnemonic

Code

Byte

Cycle

Operation

Flag

NVGBHIZC

BRK

Software interrupt : B

"1", M(sp)

(pc

), sp

sp-1,

M(s)

(pc

), sp

sp - 1, M(sp)

(PSW), sp

sp -1,

( 0FFDE

) , pc

( 0FFDF

) .

---1-0--

Disable all interrupts : I

"0"

-----0--

Enable all interrupt : I

"1"

-----1--

NOP

No operation

--------

POP A

sp + 1, A

M( sp )

POP X

sp + 1, X

M( sp )

--------

POP Y

sp + 1, Y

M( sp )

POP PSW

sp + 1, PSW

M( sp )

restored

PUSH A

M( sp )

A , sp

sp - 1

PUSH X

M( sp )

X , sp

sp - 1

--------

PUSH Y

M( sp )

Y , sp

sp - 1

PUSH PSW

M( sp )

PSW , sp

sp - 1

RET

Return from subroutine
sp

sp +1, pc

M( sp ), sp

sp +1, pc

M( sp )

--------

RETI

Return from interrupt
sp

sp +1, PSW

M( sp ), sp

sp + 1,

M( sp ), sp

sp + 1, pc

M( sp )

restored

STOP

Stop mode ( halt CPU, stop oscillator )

--------

C. MASK ORDER SHEET

MASK ORDER & VERIFICATION SHEET

GMS81C5108

1. Customer Information

Company Name

Application

Order Date

YYYY

Tel:

Fax:

Name &
Signature:

Customer should write inside thick line box.

2. Device Information

3. Marking Specification

4. Delivery Schedule

Date

Quantity

HYNIX Confirmation

YYYY

Customer sample

Risk order

pcs

E-mail address:

5. ROM Code Verification

YYYY

Verification date:

Please confirm out verification data.

Check sum:

Tel:

Fax:

Name &
Signature:

E-mail address:

YYYY

Approval date:

I agree with your verification data and confirm you to
make mask set.

Tel:

Fax:

Name &
Signature:

E-mail address:

- UD

. 2001

G M S81C 5108-U D
YYW W KO R EA

Package

80QFP

Set "00" in

this area

0000

E000

FFFF

.OTP file data

DFFF

sk Da

Hitel

Chollian

Internet

File Name : ( .OTP)
Check Sum : ( )

OSC Option

Crystal

Reset Pull Up

YES

ROM Size

G M S81C 5108-U D
YYW W KO R EA

C ustom er's Area

If the customer logo & part number must be used in this area,

(Please check mark into )

please submit a clean original logo & part number.

Hynix Sem iconductor Inc.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS87C5108

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GMS87C5108