HY57V658020B
4 Banks x 2M x 8Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 1.6/Nov. 01 1
DESCRIPTION
The Hynix HY57V658020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V658020B is organized as 4banks of 2,097,152x8.
HY57V658020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of sys-
tem clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V658020BTC-75
133MHz
Normal
4Banks x 4Mbits x4
LVTTL
400mil 54pin TSOP II
HY57V658020BTC-8
125MHz
HY57V658020BTC-10P
100MHz
HY57V658020BTC-10S
100MHz
HY57V658020BTC-10
100MHz
HY57V658020BLTC-75
133MHz
Low power
HY57V658020BLTC-8
125MHz
HY57V658020BLTC-10P
100MHz
HY57V658020BLTC-10S
100MHz
HY57V658020BLTC-10
100MHz
HY57V658020B
Rev. 1.6/Nov. 01 2
PIN CONFIGURATION
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ7
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
HY57V658020B
Rev. 1.6/Nov. 01 3
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 8 I/O Synchronous DRAM
State
M
a
c
h
ine
A0
A1
A11
BA0
BA1
Addre
s
s
bu
ffers
Address
Registers
Mode Registers
Row
Pre
Decoders
Column
Pre
Decoders
Column Add
Counter
Row active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
X de
c
o
d
e
rs
Internal Row
counter
DQ0
DQ1
DQ6
DQ7
refresh
Self refresh logic
& timer
Pipe Line Control
I/O
Buff
er & L
ogi
c
Bank Select
Sens
e AM
P & I/
O
Gat
e
CLK
CKE
CS
RAS
CAS
WE
DQM
X de
c
o
d
e
rs
X de
c
o
d
e
rs
Memory
Cell
Array
Y decoders
X de
c
o
d
e
rs
2Mx8 Bank 1
2Mx8 Bank 0
2Mx8 Bank 2
2Mx8 Bank3
HY57V658020B
Rev. 1.6/Nov. 01 4
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA=0 to 70
C)
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with
3ns of duration
3.V
IL
(min) is acceptable -2.0V AC pulse width with
3ns of duration
AC OPERATING CONDITION
(TA=0 to 70
C, V
DD
=3.3
0.3V, V
SS
=0V)
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
0 ~ 70
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
relative to V
SS
V
DD,
V
DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
1
W
Soldering Temperature
Time
T
SOLDER
260
10
C
Sec
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
1
Input High Voltage
V
IH
2.0
3.0
V
DDQ
+ 2.0
V
1,2
Input Low Voltage
V
IL
V
SSQ
- 2.0
0
0.8
V
1,3
Parameter
Symbol
Value
Unit
Note
AC Input High / Low Level Voltage
V
IH
/ V
IL
2.4/0.4
V
Input Timing Measurement Reference Level Voltage
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level
Voutref
1.4
V
Output Load Capacitance for Access Time Measurement
CL
50
pF
1
HY57V658020B
Rev. 1.6/Nov. 01 5
CAPACITANCE
(TA=25
C, f=1MHz)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I
(TA=0 to 70
C, V
DD
=3.3
0.3V)
Note :
1.V
IN
= 0 to 3.6V, All other pins are not tested under V
IN
=0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
C
I1
2
4
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM
CI
2
2.5
5
pF
Data input / output capacitance
DQ0 ~ DQ7
C
I/O
2
6.5
pF
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
I
LI
-1
1
uA
1
Output Leakage Current
I
LO
-1
1
uA
2
Output High Voltage
V
OH
2.4
-
V
I
OH
= -4mA
Output Low Voltage
V
OL
-
0.4
V
I
OL
= +4mA
Vtt=1.4V
RT=250
50pF
Output
50pF
Output
DC Output Load Circuit
AC Output Load Circuit
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