HY5DU12422(L)T
HY5DU12822(L)T
HY5DU121622(L)T
1st 512M DDR SDRAM
HY5DU12422(L)T
HY5DU12822(L)T
HY5DU121622(L)T
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6/May. 02 1
Rev. 0.6/May. 02
2
HY5DU12422(L)T
HY5DU12822(L)T
HY5DU121622(L)T
Revision History
1. Rev 0.2 (Jul. 01)
1) Preliminary IDD Specification defined
2. Rev 0.3 (Feb. 02)
1) tHZ/tLZ Specification defined
2) IDD4W Specification changed from 250mA to 200mA
3) tIS/tIH at DDR200 changed from 1.2ns to 1.1ns
3. Rev 0.4 (Feb. 02)
1) tCK max ot DDR2666A/B, DDR2000 changed 15ns to 12ns
2) tWR SPEC. at DDR200 changed 20ns to 15ns
3) IDD0 SPEC. changed from 90mA to 100mA at DDR266A/B and 85mA to 95mA at DDR200
4) tQHS at DDR200 changed from 1ns to 0.75ns
4. Rev 0.5 (May. 02)
1) IDD SPEC. updated
2) Input leakage current changed from +/-5uA to +/-2uA
5. Rev 0.6 (May. 02)
1) IDD SPEC.(IDD2Q, IDD7A) updated
DESCRIPTION
The Hynix HY5DU12422(L)T, HY5DU12822(L)T and HY5DU121622(L)T are a 536,870,912-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
The Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
V
DD
, V
DDQ
= 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable /CAS latency 1.5 / 2 / 2.5 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
Part No.
Configuration
Power
HY5DU12422T-X*
128Mx4
Standard
HY5DU12422LT-X*
128Mx4
Low Power
HY5DU12822T-X*
64Mx8
Standard
HY5DU12822LT-X*
64Mx8
Low Power
HY5DU121622T-X*
32Mx16
Standard
HY5DU121622LT-X*
32Mx16
Low Power
HY5DU12422(L)T
HY5DU12822(L)T
HY5DU121622(L)T
Rev. 0.6/May. 02 3
OPERATING FREQUENCY
* X means speed grade
** JEDEC specification compliant
Grade
CL2
CL2.5
Remark**
- K
133MHz
133MHz
DDR266A
- H
125MHz
133MHz
DDR266B
- L
100MHz
125MHz
DDR200
PRELIMINARY
Rev. 0.6/May. 02
4
HY5DU12422(L)T
HY5DU12822(L)T
HY5DU121622(L)T
PIN CONFIGURATION
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x16
x8
x4
x4
x8
x16
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
ROW AND COLUMN ADDRESS TABLE
ITEMS
128Mx4
64Mx8
32Mx16
Organization
32M x 4 x 4banks
16M x 8 x 4banks
8M x 16 x 4banks
Row Address
A0 - A12
A0 - A12
A0 - A12
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
Bank Address
BA0, BA1
BA0, BA1
BA0, BA1
Auto Precharge Flag
A10
A10
A10
Refresh
8K
8K
8K
Rev. 0.6/May. 02
5
HY5DU12422(L)T
HY5DU12822(L)T
HY5DU121622(L)T
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and
exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and
for output disable. CKE must be maintained high throughout READ and WRITE
accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an
SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection
on systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or
PRECHARGE command is being applied.
A0 ~ A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank. A10 is sampled during a precharge
command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op code during a MODE REGISTER SET com-
mand. BA0 and BA1 define which mode register is loaded during the MODE REGISTER
SET command (MRS or EMRS).
/RAS, /CAS, /
WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM
(LDM,UDM)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-
sponds to the data on DQ8-Q15.
DQS
(LDQS,UDQS)
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
DQ
I/O
Data input / output pin : Data bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
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