HY5V52CF

4 Banks x 2M x 32Bit Synchronous DRAM

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4 / June 2003

DESCRIPTION

The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32.

HY5V52CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)

FEATURES

JEDEC standard 3.3V power supply

All device pins are compatible with LVTTL interface

90Ball FBGA with 0.8mm of pin pitch

All inputs and outputs referenced to positive edge of
system clock

Data mask function by DQM0,1,2 and 3

Internal four banks operation

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY5V52(L)F-H

133MHz

4Banks x 2Mbits x32

LVTTL

90Ball FBGA

HY5V52(L)F-8

125MHz

4Banks x 2Mbits x32

LVTTL

90Ball FBGA

HY5V52(L)F-P

100MHz

4Banks x 2Mbits x32

LVTTL

90Ball FBGA

HY5V52(L)F-S

100MHz

4Banks x 2Mbits x32

LVTTL

90Ball FBGA

Preliminary

Rev. 0.4 / June 2003 3

HY5V52CF

Ball CONFIGURATION

Ball DESCRIPTION

PIN

PIN NAME

DESCRIPTION

CLK

Clock

The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1

Bank Address

Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity

A0 ~ A11

Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10

RAS, CAS, WE

Row Address Strobe,
Column Address Strobe,
Write Enable

RAS, CAS and WE define the operation
Refer function truth table for details

DQM0~3

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ31

Data Input/Output

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuits and input buffers

DDQ

SSQ

Data Output Power/Ground

Power supply for output buffers

No Connection

No connection

T o p V ie w

D Q 2 6

D Q 2 4

V S S

D Q 2 8

V D D Q

V S S Q

D Q 2 7

D Q 2 5

V S S Q

D Q 2 9

D Q 3 0

V D D Q

D Q 3 1

N C

V S S

D Q M 3

A 3

A 4

A 5

A 6

A 7

A 8

N C

C L K

C K E

A 9

D Q M 1

N C

V D D Q

D Q 8

V S S

V S S Q

D Q 1 0

D Q 9

V S S Q

D Q 1 2

D Q 1 4

D Q 1 1

V D D Q

V S S Q

D Q 1 3

D Q 1 5

V S S

V D D

D Q 2 3

D Q 2 1

V D D Q

V S S Q

D Q 1 9

D Q 2 2

D Q 2 0

V D D Q

D Q 1 7

D Q 1 8

V D D Q

N C

D Q 1 6

V S S Q

A 2

D Q M 2

V D D

A 1 0

A 0

A 1

N C

B A 1

A 1 1

B A 0

/C S

/R A S

/C A S

/W E

D Q M 0

V D D

D Q 7

V S S Q

D Q 6

D Q 5

V D D Q

D Q 1

D Q 3

V D D Q

V S S Q

D Q 4

V D D

D Q 0

D Q 2

T o p V ie w

D Q 2 6

D Q 2 4

V S S

D Q 2 8

V D D Q

V S S Q

D Q 2 7

D Q 2 5

V S S Q

D Q 2 9

D Q 3 0

V D D Q

D Q 3 1

N C

V S S

D Q M 3

A 3

A 4

A 5

A 6

A 7

A 8

N C

C L K

C K E

A 9

D Q M 1

N C

V D D Q

D Q 8

V S S

V S S Q

D Q 1 0

D Q 9

V S S Q

D Q 1 2

D Q 1 4

D Q 1 1

V D D Q

V S S Q

D Q 1 3

D Q 1 5

V S S

V D D

D Q 2 3

D Q 2 1

V D D Q

V S S Q

D Q 1 9

D Q 2 2

D Q 2 0

V D D Q

D Q 1 7

D Q 1 8

V D D Q

N C

D Q 1 6

V S S Q

A 2

D Q M 2

V D D

A 1 0

A 0

A 1

N C

B A 1

A 1 1

B A 0

/C S

/R A S

/C A S

/W E

D Q M 0

V D D

D Q 7

V S S Q

D Q 6

D Q 5

V D D Q

D Q 1

D Q 3

V D D Q

V S S Q

D Q 4

V D D

D Q 0

D Q 2

D Q 2 6

D Q 2 4

V S S

D Q 2 8

V D D Q

V S S Q

D Q 2 7

D Q 2 5

V S S Q

D Q 2 9

D Q 3 0

V D D Q

D Q 3 1

N C

V S S

D Q M 3

A 3

A 4

A 5

A 6

A 7

A 8

N C

C L K

C K E

A 9

D Q M 1

N C

V D D Q

D Q 8

V S S

V S S Q

D Q 1 0

D Q 9

V S S Q

D Q 1 2

D Q 1 4

D Q 1 1

V D D Q

V S S Q

D Q 1 3

D Q 1 5

V S S

V D D

D Q 2 3

D Q 2 1

V D D Q

V S S Q

D Q 1 9

D Q 2 2

D Q 2 0

V D D Q

D Q 1 7

D Q 1 8

V D D Q

N C

D Q 1 6

V S S Q

A 2

D Q M 2

V D D

A 1 0

A 0

A 1

N C

B A 1

A 1 1

B A 0

/C S

/R A S

/C A S

/W E

D Q M 0

V D D

D Q 7

V S S Q

D Q 6

D Q 5

V D D Q

D Q 1

D Q 3

V D D Q

V S S Q

D Q 4

V D D

D Q 0

D Q 2

D Q 2 6

D Q 2 4

V S S

D Q 2 8

V D D Q

V S S Q

D Q 2 7

D Q 2 5

V S S Q

D Q 2 9

D Q 3 0

V D D Q

D Q 3 1

N C

V S S

D Q M 3

A 3

A 4

A 5

A 6

A 7

A 8

N C

C L K

C K E

A 9

D Q M 1

N C

V D D Q

D Q 8

V S S

V S S Q

D Q 1 0

D Q 9

V S S Q

D Q 1 2

D Q 1 4

D Q 1 1

V D D Q

V S S Q

D Q 1 3

D Q 1 5

V S S

V D D

D Q 2 3

D Q 2 1

V D D Q

V S S Q

D Q 1 9

D Q 2 2

D Q 2 0

V D D Q

D Q 1 7

D Q 1 8

V D D Q

N C

D Q 1 6

V S S Q

A 2

D Q M 2

V D D

A 1 0

A 0

A 1

N C

B A 1

A 1 1

B A 0

/C S

/R A S

/C A S

/W E

D Q M 0

V D D

D Q 7

V S S Q

D Q 6

D Q 5

V D D Q

D Q 1

D Q 3

V D D Q

V S S Q

D Q 4

V D D

D Q 0

D Q 2

D Q 2 6

D Q 2 4

V S S

D Q 2 8

V D D Q

V S S Q

D Q 2 7

D Q 2 5

V S S Q

D Q 2 9

D Q 3 0

V D D Q

D Q 3 1

N C

V S S

D Q M 3

A 3

A 4

A 5

A 6

A 7

A 8

N C

C L K

C K E

A 9

D Q M 1

N C

V D D Q

D Q 8

V S S

V S S Q

D Q 1 0

D Q 9

V S S Q

D Q 1 2

D Q 1 4

D Q 1 1

V D D Q

V S S Q

D Q 1 3

D Q 1 5

V S S

V D D

D Q 2 3

D Q 2 1

V D D Q

V S S Q

D Q 1 9

D Q 2 2

D Q 2 0

V D D Q

D Q 1 7

D Q 1 8

V D D Q

N C

D Q 1 6

V S S Q

A 2

D Q M 2

V D D

A 1 0

A 0

A 1

N C

B A 1

A 1 1

B A 0

/C S

/R A S

/C A S

/W E

D Q M 0

V D D

D Q 7

V S S Q

D Q 6

D Q 5

V D D Q

D Q 1

D Q 3

V D D Q

V S S Q

D Q 4

V D D

D Q 0

D Q 2

Rev. 0.4 / June 2003 4

HY5V52CF

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION

(TA=0 to 70

°C)

Note :
1.All voltages are referenced to V

= 0V

2.V

(max) is acceptable 5.6V AC pulse width with

3ns of duration with no input clamp diodes

3.V

(min) is acceptable -2.0V AC pulse width with

3ns of duration with no input clamp diodes

AC OPERATING CONDITION

(TA=0 to 70

°C, 3.0V V

3.6V, V

=0V - Note1)

Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

°C

Storage Temperature

STG

-55 ~ 125

°C

Voltage on Any Pin relative to V

, V

OUT

-1.0 ~ 4.6

Voltage on V

relative to V

DD,

DDQ

-1.0 ~ 4.6

Short Circuit Output Current

Power Dissipation

Soldering Temperature

Time

SOLDER

260

°C Sec

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

, V

DDQ

3.135

3.3

3.6

Input high voltage

2.0

3.0

DDQ

+ 0.3

1,2

Input low voltage

SSQ

- 0.3

0.8

1,3

Parameter

Symbol

Value

Unit

Note

AC input high / low level voltage

/ V

2.4/0.4

Input timing measurement reference level voltage

Vtrip

1.4

Input rise / fall time

tR / tF

Output timing measurement reference level

Voutref

1.4

Output load capacitance for access time measurement

Rev. 0.4 / June 2003 6

HY5V52CF

DC CHARACTERISTICS II

(DC operating conditions unless otherwise noted)

Note :

1.I

DD1

and I

DD4

depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY5V52CF-H/8/P/S
4.HY5V52CL:F-H/8/P/S

Parameter

Symbol

Test Condition

speed

Unit

Note

-H

-8

-P

Operating Current

IDD1

Burst length=1, One bank active
t

(min), I

=0mA

240

220

Precharge Standby
Current
in power down mode

IDD2P

CKE

(max), t

= 10ns

IDD2PS

CKE

(max), t

Precharge Standby
Current
in non power down mode

IDD2N

CKE

(min), CS

(min), t

= 10ns

Input signals are changed one time during
2clks. All other pins

VDD-0.2V or 0.2V

IDD2NS

CKE

(min), t

Input signals are stable.

Active Standby Current
in power down mode

IDD3P

CKE

(max), t

= 10ns

IDD3PS

CKE

(max), t

Active Standby Current
in non power down mode

IDD3N

CKE

(min), CS

(min), t

= 10ns

Input signals are changed one time during
2clks. All other pins

-0.2V or

0.2V

IDD3NS

CKE

(min), t

Input signals are stable.

Burst Mode Operating
Current

IDD4

(min), I

=0mA

All banks active

CL=3

260

220

CL=2

280

240

Auto Refresh Current

IDD5

(min), All banks active

440

400

Self Refresh Current

IDD6

CKE

0.2V

1.6

Rev. 0.4 / June 2003 7

HY5V52CF

AC CHARACTERISTICS I

(AC operating conditions unless otherwise noted)

Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v

Data-out hold time to be measured under 30pF load condition, without Vt termination

Parameter

Symbol

-H

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

System clock
cycle time

CAS Latency = 3

tCK3

7.5

1000

CAS Latency = 2

tCK2

-10

Clock high pulse width

tCHW

Clock low pulse width

tCLW

Access time from clock

CAS Latency = 3

tAC3

5.5

CAS Latency = 2

tAC2

Data-out hold time

tOH

Data-Input setup time

tDS

1.75

Data-Input hold time

tDH

Address setup time

tAS

1.75

Address hold time

tAH

CKE setup time

tCKS

1.75

CKE hold time

tCKH

Command setup time

tCS

1.75

Command hold time

tCH

CLK to data output in low Z-time

tOLZ

CLK to data output in
high Z-time

CAS Latency = 3

tOHZ3

5.5

CAS Latency = 2

tOHZ2

Rev. 0.4 / June 2003 8

HY5V52CF

AC CHARACTERISTICS II

(AC operating conditions unless otherwise noted)

Parameter

Symbol

-H

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

RAS cycle time

Operation

tRC

Auto Refresh

tRRC

RAS to CAS delay

tRCD

RAS active time

tRAS

100K

RAS precharge time

tRP

RAS to RAS bank active delay

tRRD

CLK

CAS to CAS delay

tCCD

CLK

Write command to data-in delay

tWTL

CLK

Data-in to precharge command

tDPL

CLK

Data-in to active command

tDAL

CLK

DQM to data-out Hi-Z

tDQZ

CLK

DQM to data-in mask

tDQM

CLK

MRS to new command

tMRD

CLK

Precharge to data
output Hi-Z

CAS Latency = 3

tPROZ3

CLK

CAS Latency = 2

tPROZ2

CLK

Power down exit time

tPDE

CLK

Self refresh exit time

tSRE

CLK

Refresh Time

tREF

Note :

1. A new command can be given tRRC after self refresh exit

Rev. 0.4 / June 2003 9

HY5V52CF

COMMAND TRUTH TABLE

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don

t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.

Command

CKEn-1

CKEn

RAS

CAS

DQM

ADDR

A10/

Note

Mode Register Set

OP code

No Operation

Bank Active

Read

Read with Autoprecharge

Write

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

DQM

Auto Refresh

Burst-Read-Single-
WRITE

A9 Pin High

(Other Pins OP code)

MRS

Mode

Self Refresh

Entry

Exit

Precharge
power down

Entry

Exit

Clock
Suspend

Entry

Exit

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