Document Outline
- Revision History
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- Ball CONFIGURATION
- Ball FUNCTION DESCRIPTIONS
- FUNCTIONAL BLOCK DIAGRAM
- BASIC FUNCTIONAL DESCRIPTION
- ABSOLUTE MAXIMUM RATING
- DC OPERATING CONDITION
- AC OPERATING TEST CONDITION
- CAPACITANCE
- DC CHARACTERRISTICS I
- DC CHARACTERISTICS II
- AC CHARACTERISTICS I
- AC CHARACTERISTICS II
- COMMAND TRUTH TABLE
- PACKAGE INFORMATION
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / June. 2004
1
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
Document Title
4Bank x 2M x 32bits Synchronous DRAM
Revision History
Revision No.
History
Draft Date
Remark
0.1
Initial Draft
Jun. 2004
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / June. 2004
2
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32.
HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
ORDERING INFORMATION
Note
1. HY5V52F Series : Normal power
2. HY5V52LF Series : Low Power
3. HY5V52xF Series : Leaded 90Ball FBGA
4. HY5V52xFP Series : Lead Free 90Ball FBGA
Part No.
Clock
Frequency
CAS
Latency
Organization
Interface
90 Ball FBGA
HY5V52(L)F-H
133MHz
3
4Banks x 2Mbits
x32
LVTTL
Leaded
HY5V52(L)F-P
100MHz
2
HY5V52(L)F-S
100MHz
3
HY5V52(L)FP-H
133MHz
3
Lead Free
HY5V52(L)FP-P
100MHz
2
HY5V52(L)FP-S
100MHz
3
Voltage : VDD, VDDQ 3.3V
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
Rev. 0.1 / June. 2004
3
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
Ball CONFIGURATION
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQS
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
/CAS
VDD
DQ6
DQ1
VDDQ
VDD
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQS
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
/CAS
VDD
DQ6
DQ1
VDDQ
VDD
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
VDDQ
CKE
NC
DQS
DQ10
DQ12
VDDQ
DQ15
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
/CAS
VDD
DQ6
DQ1
VDDQ
VDD
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
/WE
DQ7
DQ5
DQ3
VSSQ
DQ0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
/RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
1
1
2
2
3
3
7
7
8
8
9
9
4
4
5
5
6
6
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
TOP
View
Rev. 0.1 / June. 2004
4
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
Ball FUNCTION DESCRIPTIONS
SYMBOL
Ball NAME
TYPE
DESCRIPTION
CLK
Clock
INPUT
The system clock input. All other inputs are registered to the SDRAM on
the rising edge of CLK.
CKE
Clock Enable
INPUT
Controls internal clock signal and when deactivated, the SDRAM will be
one of the states among power down, suspend or self refresh
CS
Chip Select
INPUT
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
INPUT
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
INPUT
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS,
WE
Row Address
Strobe,
Column Address
Strobe, Write
Enable
INPUT
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output
Mask
I/O
Controls output buffers in read mode and masks input data in write
mode
DQ0 ~
DQ31
Data Input/Output
SUPPLY Multiplexed data input / output pin
NC
No Connection
-
No Connection
Rev. 0.1 / June. 2004
5
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 32 I/O Synchronous DRAM
Internal Row
Counter
Column
Pre
Decoder
Column Add
Counter
Self refresh
logic & timer
Sens
e AMP & I/O Gate
I
/
O
B
u
ffe
r &
Lo
gic
Address
Register
Burst
Counter
Mode Register
S
t
at
e M
a
chi
n
e
A
dd
re
ss Buff
ers
Bank Select
Column Active
Row Active
CAS Latency
CLK
CKE
CS
RAS
CAS
WE
DQM0
A0
A1
BA1
BA0
A11
Row
Pre
Decoder
Refresh
DQ0
DQ31
X-
Decod
e
r
X-Dec
o
de
r
X
-
Decod
er
X-
Decod
e
r
Y-Decoder
2Mx32 BANK 0
2Mx32 BANK 1
2Mx32 BANK 2
2Mx32 BANK 3
Memory
Cell
Array
Data Out Control
DQM1
DQM2
DQM3
Pipe Line
Control
Rev. 0.1 / June. 2004
6
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
OP Code
0
0
CAS Latency
BT
Burst Length
OP Code
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
Burst Type
A3
Burst Type
0
Sequential
1
Interleave
Burst Length
A2
A1
A0
Burst Length
A3 = 0
A3=1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
CAS Latency
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Rev. 0.1 / June. 2004
7
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
ABSOLUTE MAXIMUM RATING
DC OPERATING CONDITION
(T
A
= 0 to 70
o
C
)
Note :
1. All voltages are referenced to V
SS
= 0V
2. V
IH
(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3. V
IL
(min) is acceptable -2.0V AC pulse width with <=3ns of duration
AC OPERATING TEST CONDITION
(T
A
= 0 to 70
o
C, V
DD
=3.3
0.3V, V
SS
=0V)
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
0 ~ 70
o
C
Storage Temperature
T
STG
-55 ~ 125
o
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
relative to V
SS
V
DD
-1.0 ~ 4.6
V
Voltage on V
DDQ
relative to V
SS
V
DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature
.
Time
T
SOLDER
260
.
10
o
C
.
Sec
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
V
DD,
V
DDQ
3.0
3.3
3.6
V
1
Input High Voltage
V
IH
2.0
3.3
V
DDQ+
0.3
V
1, 2
Input Low Voltage
V
IL
-0.3
-
0.8
V
1, 3
Parameter
Symbol
Value
Unit
Note
AC Input High/Low Level Voltage
V
IH
/ V
IL
2.4/0.4
V
Input Timing Measurement Reference Level Voltage
V
trip
1.4
V
Input Rise/Fall Time
t
R
/ t
F
1
ns
Output Timing Measurement Reference Level Voltage
V
outref
1.4
V
Output Load Capacitance for Access Time Measurement
CL
50
pF
1
Rev. 0.1 / June. 2004
8
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
CAPACITANCE
(T
A
= 0 to 70
o
C, f=1MHz, V
DD
=3.3V)
Note 1.
DC CHARACTERRISTICS I
(T
A
= 0 to 70
o
C)
Note :
1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 3.6
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
CI1
2.0
4.0
pF
A0 ~ A12, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
CI2
2.0
4.0
pF
Data input / output capaci-
tance
DQ0 ~ DQ31
CI/O
3.5
6.5
pF
Parameter
Symbol
Min
Max
Unit
Note
Input Leakage Current
I
LI
-1
1
uA
1
Output Leakage Current
I
LO
-1
1
uA
2
Output High Voltage
V
OH
2.4
-
V
I
OH
= -2mA
Output Low Voltage
V
OL
-
0.4
V
I
OL
= +2mA
Vtt=1.4V
RT=500
30pF
Output
DC Output Load Circuit
AC Output Load Circuit
Vtt=1.4V
RT=50
30pF
Output
Z0 = 50
Rev. 0.1 / June. 2004
9
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
DC CHARACTERISTICS II
(T
A
= 0 to 70
o
C)
Note :
1. I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY5V52F(P) Series : Normal, HY5V52LF(P) Series : Low Power
Parameter
Symbol
Test Condition
Speed
Uni
t
Not
e
H
P
S
Operating Current
I
DD1
Burst length=1, One bank active
t
RC
t
RC
(min), I
OL
=0mA
120
110
mA
1
Precharge Standby Current
in Power Down Mode
I
DD2P
CKE
V
IL
(max), t
CK
= 15ns
2
mA
I
DD2PS
CKE
V
IL
(max), t
CK
=
1
mA
Precharge Standby Current
in Non Power Down Mode
I
DD2N
CKE
V
IH
(min), CS
V
IH
(min), t
CK
= 15ns
Input signals are changed one time during
2clks.
All other pins
V
DD
-0.2V or
0.2V
15
mA
I
DD2NS
CKE
V
IH
(min), t
CK
=
Input signals are stable.
15
Active Standby Current
in Power Down Mode
I
DD3P
CKE
V
IL
(max), t
CK
= 15ns
5
mA
I
DD3PS
CKE
V
IL
(max), t
CK
=
5
Active Standby Current
in Non Power Down Mode
I
DD3N
CKE
V
IH
(min), CS
V
IH
(min), t
CK
= 15ns
Input signals are changed one time during
2clks.
All other pins
V
DD
-0.2V or
0.2V
30
mA
I
DD3NS
CKE
V
IH
(min), t
CK
=
Input signals are stable.
20
Burst Mode Operating Cur-
rent
I
DD4
t
CK
t
CK
(min), I
OL
=0mA
All banks active
CL=3
150
130
mA
1
CL=2
160
140
Auto Refresh Current
I
DD5
t
RC
t
RC
(min), All banks active
220
mA
2
Self Refresh Current
I
DD6
CKE
0.2V
Normal
3
mA
3
Low Power
1.5
Rev. 0.1 / June. 2004
10
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1. Assume t
R
/ t
F
(input rise and fall time) is 1ns. If t
R
& t
F
> 1ns, then [(t
R
+t
F
)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If t
R
> 1ns,
then (t
R
/2-0.5)ns should be added to the parameter.
Parameter
Symbol
H
P
S
Unit Note
Min Max Min Max Min Max
System ClockCycle Time
CAS Latency=3
t
CK3
7.5
1000
10
1000
10
1000
ns
CAS Latency=2
t
CK2
10
10
12
ns
Clock High Pulse Width
t
CHW
2.5
-
3.0
-
3.0
-
ns
1
Clock Low Pulse Width
t
CLW
2.5
-
3.0
-
3.0
-
ns
1
Access Time From Clock
CAS Latency=3
t
AC3
-
5.4
-
6
-
6
ns
2
CAS Latency=2
t
AC2
-
6
-
6
-
6
ns
Data-out Hold Time
t
OH
2.0
-
2.0
-
2.0
-
ns
Data-Input Setup Time
t
DS
2.0
-
2.0
-
2.0
-
ns
1
Data-Input Hold Time
t
DH
1.0
-
1.0
-
1.0
-
ns
1
Address Setup Time
t
AS
2.0
-
2.0
-
2.0
-
ns
1
Address Hold Time
t
AH
1.0
-
1.0
-
1.0
-
ns
1
CKE Setup Time
t
CKS
2.0
-
2.0
-
2.0
-
ns
1
CKE Hold Time
t
CKH
1.0
-
1.0
-
1.0
-
ns
1
Command Setup Time
t
CS
2.0
-
2.0
-
2.0
-
ns
1
Command Hold Time
t
CH
1.0
-
1.0
-
1.0
-
ns
1
CLK to Data Output in Low-Z Time
t
OLZ
1.0
-
1.0
-
1.0
-
ns
CLK to Data Output in High-
Z Time
CAS Latency=3
t
OHZ3
2.0
5.4
2.0
6.0
2.0
6.0
ns
CAS Latency=2
t
OHZ2
2.0
6.0
2.0
6.0
2.0
6.0
ns
Rev. 0.1 / June. 2004
11
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note :
1. A new command can be given t
RC
after self refresh exit.
Parameter
Symbol
H
P
S
Unit Note
Min Max Min Max Min Max
RAS Cycle Time
Operation
t
RC
65
-
70
-
70
-
ns
RAS Cycle Time
Auto Refresh
t
RRC
65
-
70
-
70
-
ns
RAS to CAS Delay
t
RCD
20
-
20
-
20
-
ns
RAS Active Time
t
RAS
45 100K 50 100K 50 100K ns
RAS Precharge Time
t
RP
20
-
20
-
20
-
ns
RAS to RAS Bank Active Delay
t
RRD
15
-
20
-
20
-
ns
CAS to CAS Delay
t
CCD
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
t
WTL
0
-
0
-
0
-
CLK
Data-in to Precharge Command
t
DPL
2
-
2
-
2
-
CLK
Data-In to Active Command
t
DAL
t
DPL
+ t
RP
DQM to Data-Out Hi-Z
t
DQZ
2
-
2
-
2
-
CLK
DQM to Data-In Mask
t
DQM
0
-
0
-
0
-
CLK
MRS to New Command
t
MRD
2
-
2
-
2
-
CLK
Precharge to Data Output
High-Z
CAS Latency=3
t
PROZ3
3
-
3
-
3
-
CLK
CAS Latency=2
t
PROZ2
2
-
2
-
2
-
CLK
Power Down Exit Time
t
DPE
1
-
1
-
1
-
CLK
Self Refresh Exit Time
t
SRE
1
-
1
-
1
-
CLK
1
Refresh Time
t
REF
-
64
-
64
-
64
ms
Rev. 0.1 / June. 2004
12
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-Read-Single-WRITE
H
X
L
L
L
L
X
A9 ball High
(Other balls OP code)
MRS
Mode
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge
power down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
Rev. 0.1 / June. 2004
13
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
PACKAGE INFORMATION
90 Ball 0.8mm pitch, 11mm x 13mm FBGA
Unit [mm]
1.20 max
0.340 0.05
0.450 0.05
11.0
6.40 BSC
0.80( Typ)
A1 INDEX MARK
13.0
0.10
11.20
B
S
C
0.80( Typ)
6.50
0.05
3.20 0.05
5.50 0.05
Bottom
Bottom
View
View
2.30 0.10
0.80(
6.50
0.05
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