HY5V56B(L/S)F Series

4 Banks x 4M x 16bits Synchronous DRAM

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1/Oct. 02 2

DESCRIPTION

Preliminary

The HY5V56B(L)F is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which
require low power consumption and industrial temperature range. HY5V56B(L)F is organized as 4banks of
4,194,304x16

HY5V56B(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)

FEATURES

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY5V56BF-H

133MHz

Normal

4Banks x 4Mbits

x16

LVTTL

54ball FBGA

HY5V56BF-8

125MHz

HY5V56BF-P

100MHz

HY5V56BF-S

100MHz

HY5V56B(L)F-H

133MHz

Low power

HY5V56B(L)F-8

125MHz

HY5V56B(L)F-P

100MHz

HY5V56B(L)F-S

100MHz

Single 3.3±0.3V power supply

All device balls are compatible with LVTTL interface

54Ball FBGA (13.5mm x 8.0mm)

All inputs and outputs referenced to positive edge of
system clock

Data mask function by UDQM or LDQM

Internal four banks operation

Auto refresh and self refresh

8192 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 3

BALL CONFIGURATION

54 Ball
FBGA
0.8 mm
Ball Pitch

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

CLK

VSS

UDQM

A11

CKE

A12

VSS

VDDQ

VSSQ

VDD

DQ0

VDD

DQ2

DQ1

DQ4

DQ3

DQ6

DQ5

DQ7

LDQM

/CAS

/RAS

/WE

A10

/CS

BA0

BA1

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HY5V56B(L/S)F

BALL DESCRIPTION

BALL OUT

SYMBOL

TYPE

DESCRIPTION

CLK

INPUT

Clock : The system clock input. All other inputs are registered
to the SDRAM on the rising edge of CLK

CKE

INPUT

Clock Enable : Controls internal clock signal and when deacti-
vated, the SDRAM will be one of the states among power
down, suspend or self refresh

INPUT

Chip Select : Enables or disables all inputs except CLK, CKE,
UDQM and LDQM

G7,G8

BA0, BA1

INPUT

Bank Address : Selects bank to be activated during RAS activ-
ity
Selects bank to be read/written during CAS activity

H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2,
G1

A0 ~ A12

INPUT

Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag : A10

F8, F7, F9

RAS, CAS,
WE

INPUT

Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details

F1, E8

UDQM,
LDQM

INPUT

Data Mask:Controls output buffers in read mode and masks
input data in write mode

A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2

DQ0 ~
DQ15

I/O

Data Input/Output:Multiplexed data input/output ball

A9, E7, J9, A1,
E3, J1

VDD/VSS

SUPPLY

Power supply for internal circuits

A7, B3, C7, D3,
A3, B7, C3, D7

VDDQ/
VSSQ

SUPPLY

Power supply for output buffers

E2, G1

No connection

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 5

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x 16 I/O Synchronous DRAM

de
code

r
s

e M
a
ch

i
n
e

A0
A1

A11

BA0
BA1

Addr

ess b

u
ff

e
r
s

Address
Registers

Mode Registers

Row

Pre

Decoders

Column

Pre

Decoders

Column Add

Counter

Row active

Column
Active

Burst

Counter

Data Out Control

CAS Latency

Internal Row

counter

DQ0

DQ1

DQ14

DQ15

refresh

Self refresh logic

& timer

Pipe Line Control

I/O Buff

e
r

& L
ogic

Bank Select

Sens

e AM

P &
I/

O Gate

CLK

CKE

RAS

CAS

UDQM

LDQM

4Mx16 Bank 3

X d
e
c
o
d
e
r
s

Memory

Cell

Array

Y decoders

de
code

r
s

4Mx16 Bank 0

4Mx16 Bank 1

4Mx16 Bank 2

de
code

r
s

de
code

r
s

e M
a
ch

i
n
e

A0
A1

A12

BA0
BA1

Addr

ess b

u
ff

e
r
s

Address
Registers

Mode Registers

Row

Pre

Decoders

Column

Pre

Decoders

Column Add

Counter

Row active

Column
Active

Burst

Counter

Data Out Control

CAS Latency

Internal Row

counter

DQ0

DQ1

DQ14

DQ15

refresh

Self refresh logic

& timer

Pipe Line Control

I/O Buff

e
r

& L
ogic

Bank Select

Sens

e AM

P &
I/

O Gate

CLK

CKE

RAS

CAS

UDQM

LDQM

4Mx16 Bank 3

X d
e
c
o
d
e
r
s

Memory

Cell

Array

Y decoders

de
code

r
s

Memory

Cell

Array

Y decoders

de
code

r
s

4Mx16 Bank 0

4Mx16 Bank 1

4Mx16 Bank 2

de
code

r
s

de
code

r
s

e M
a
ch

i
n
e

A0
A1

A11

BA0
BA1

Addr

ess b

u
ff

e
r
s

Address
Registers

Mode Registers

Row

Pre

Decoders

Column

Pre

Decoders

Column Add

Counter

Row active

Column
Active

Burst

Counter

Data Out Control

CAS Latency

Internal Row

counter

DQ0

DQ1

DQ14

DQ15

refresh

Self refresh logic

& timer

Pipe Line Control

I/O Buff

e
r

& L
ogic

Bank Select

Sens

e AM

P &
I/

O Gate

CLK

CKE

RAS

CAS

UDQM

LDQM

4Mx16 Bank 3

X d
e
c
o
d
e
r
s

Memory

Cell

Array

Y decoders

de
code

r
s

Memory

Cell

Array

Y decoders

de
code

r
s

4Mx16 Bank 0

4Mx16 Bank 1

4Mx16 Bank 2

de
code

r
s

de
code

r
s

e M
a
ch

i
n
e

A0
A1

A12

BA0
BA1

Addr

ess b

u
ff

e
r
s

Address
Registers

Mode Registers

Row

Pre

Decoders

Column

Pre

Decoders

Column Add

Counter

Row active

Column
Active

Burst

Counter

Data Out Control

CAS Latency

Internal Row

counter

DQ0

DQ1

DQ14

DQ15

refresh

Self refresh logic

& timer

Pipe Line Control

I/O Buff

e
r

& L
ogic

Bank Select

Sens

e AM

P &
I/

O Gate

CLK

CKE

RAS

CAS

UDQM

LDQM

4Mx16 Bank 3

X d
e
c
o
d
e
r
s

Memory

Cell

Array

Y decoders

de
code

r
s

Memory

Cell

Array

Y decoders

de
code

r
s

4Mx16 Bank 0

4Mx16 Bank 1

4Mx16 Bank 2

Memory

Cell

Array

Y decoders

de
code

r
s

Memory

Cell

Array

Y decoders

de
code

r
s

4Mx16 Bank 0

4Mx16 Bank 1

4Mx16 Bank 2

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 6

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION

= 0

°C to 70°C)

Note :
1.All voltages are referenced to V

= 0V

2.V

(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3.V

(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION

= 0

°C to 70°C, V

=3.3

0.3V, V

=0V)

Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

°C

Storage Temperature

STG

-55 ~ 125

°C

Voltage on Any ball relative to V

, V

OUT

-1.0 ~ 4.6

Voltage on V

relative to V

DD,

DDQ

-1.0 ~ 4.6

Short Circuit Output Current

Power Dissipation

Soldering Temperature

Time

SOLDER

260

°C Sec

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

, V

DDQ

3.0

3.3

3.6

Input High voltage

2.0

3.0

DDQ

+ 0.3

1,2

Input Low voltage

-0.3

0.8

1,3

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

/ V

2.4/0.4

Input Timing Measurement Reference Level Voltage

Vtrip

1.4

Input Rise / Fall Time

tR / tF

Output Timing Measurement Reference Level Voltage

Voutref

1.4

Output Load Capacitance for Access Time Measurement

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 7

CAPACITANCE

(TA=25

°C, f=1MHz)

OUTPUT LOAD CIRCUIT

DC CHARACTERISTICS I

(TA= 0

°C to 70°C, V

=3.3

0.3V)

Note :

1.V

= 0 to 3.6V, All other balls are not tested under V

=0V

2.D

OUT

is disabled, V

OUT

=0 to 3.6

Parameter

ball

Symbol

-H

-8/P/S

Unit

Min

Max

Min

Max

Input capacitance

CLK

2.5

3.5

2.5

4.0

A0 ~ A12, BA0, BA1, CKE, CS, RAS,
CAS, WE, UDQM, LDQM

2.5

3.8

2.5

5.0

Data input / output capaci-
tance

DQ0 ~ DQ15

I/O

4.0

6.5

4.0

6.5

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

-1

Output Leakage Current

-1

Output High Voltage

2.4

= -2mA

Output Low Voltage

0.4

= +2mA

Vtt=1.4V

RT=250

50pF

Output

50pF

Output

DC Output Load Circuit

AC Output Load Circuit

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 8

DC CHARACTERISTICS II

(TA= 0

°C to 70°C, V

=3.3

0.3V, V

=0V)

Note :
1.I

DD1

and I

DD4

depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY5V56BF-H/8/P/S
4.HY5V56BLF-H/8/P/S
5.HY5V56BSF-H/8/P/S

Parameter

Symbol

Test Condition

Unit

Note

-H

-8

-P

-S

Operating Current

DD1

Burst length=1, One bank active
t

(min), I

=0mA

120

110

Precharge Standby Current
in Power Down Mode

DD2P

CKE

(max), t

= 15ns

DD2PS

CKE

(max), t

Precharge Standby Current
in Non Power Down Mode

DD2N

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during
30ns. All other balls

-0.2V or

0.2V

DD2NS

CKE

(min), t

Input signals are stable.

Active Standby Current
in Power Down Mode

DD3P

CKE

(max), t

= 15ns

DD3PS

CKE

(max), t

Active Standby Current
in Non Power Down Mode

DD3N

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during
30ns. All other balls

-0.2V or

0.2V

DD3NS

CKE

(min), t

Input signals are stable.

Burst Mode Operating
Current

DD4

(min), I

=0mA

All banks active

CL=3

130

110

CL=2

140

120

Auto Refresh Current

DD5

RRC

(min), All banks active

220

200

Self Refresh Current

DD6

CKE

0.2V

Normal

Low Power

1.5

SL Power

800

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 9

AC CHARACTERISTICS I

(AC operating conditions unless otherwise noted)

Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter

Parameter

Symbol

-H

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

System Clock Cycle
Time

CAS Latency = 3

tCK3

7.5

1000

CAS Latency = 2

tCK2

Clock High Pulse Width

tCHW

2.5

Clock Low Pulse Width

tCLW

2.5

Access Time From
Clock

CAS Latency = 3

tAC3

5.4

CAS Latency = 2

tAC2

Data-Out Hold Time

tOH

2.5

Data-Input Setup Time

tDS

Data-Input Hold Time

tDH

0.8

Address Setup Time

tAS

1.5

Address Hold Time

tAH

0.8

CKE Setup Time

tCKS

1.5

CKE Hold Time

tCKH

0.8

Command Setup Time

tCS

1.5

Command Hold Time

tCH

0.8

CLK to Data Output in Low-Z Time

tOLZ

CLK to Data Output in
High-Z Time

CAS Latency = 3

tOHZ3

2.0

5.4

2.0

CAS Latency = 2

tOHZ2

2.0

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 10

AC CHARACTERISTICS II

Note :
1. A new command can be given tRRC after self refresh exit

Parameter

Symbol

-H

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

RAS Cycle Time

Operation

tRC

Auto Refresh

tRRC

RAS to CAS Delay

tRCD

RAS Active Time

tRAS

100K

RAS Precharge Time

tRP

RAS to RAS Bank Active Delay

tRRD

CAS to CAS Delay

tCCD

CLK

Write Command to Data-In Delay

tWTL

CLK

Data-In to Precharge Command

tDPL

CLK

Data-In to Active Command

tDAL

CLK

DQM to Data-Out Hi-Z

tDQZ

CLK

DQM to Data-In Mask

tDQM

CLK

MRS to New Command

tMRD

CLK

Precharge to Data
Output Hi-Z

CAS Latency = 3

tPROZ3

CLK

CAS Latency = 2

tPROZ2

CLK

Power Down Exit Time

tPDE

CLK

Self Refresh Exit Time

tSRE

CLK

Refresh Time

tREF

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 11

IBIS SPECIFICATION

Characteristics (Pull-up)

Characteristics (Pull-down)

Voltage

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

(V)

I(mA)

3.45

-2.4

3.3

-27.3

3.0

-74.1

-0.7

2.6

-21.1

-129.2

-7.5

2.4

-34.1

-153.3

-13.3

2.0

-58.7

-197

-27.5

1.8

-67.3

-226.2

-35.5

1.65

-73

-248

-41.1

1.5

-77.9

-269.7

-47.9

1.4

-80.8

-284.3

-52.4

1.0

-88.6

-344.5

-72.5

-93

-502.4

-93

Voltage

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

(V)

I(mA)

0.4

27.5

70.2

17.7

0.65

41.8

107.5

26.9

0.85

51.6

133.8

33.3

1.0

58.0

151.2

37.6

1.4

70.7

187.7

46.6

1.5

72.9

194.4

48.0

1.65

75.4

202.5

49.5

1.8

77.0

208.6

50.7

1.95

77.6

212.0

51.5

3.0

80.3

219.6

54.2

3.45

81.4

222.6

54.9

-600

-500

-400

-300

-200

-100

0.5

1.5

2.5

3.5

Voltage (V)

I (mA)

Min (66MHz)

Min (100MHz)

Max (66 /100MHz)

66MHz and 100MHz Pull-up

100

150

200

250

0.5

1.5

2.5

3.5

Voltage (V)

I (mA)

66MHz and 100MHz Pull-down

Min (100MHz)

Min (66MHz)

Max (100MHz)

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 12

DEVICE OPERATING OPTION TABLE

HY5V56B(L)F-H

HY5V56B(L)F-8

HY5V56B(L)F-P

HY5V56B(L)F-S

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

3CLKs

6CLKs

9CLKs

3CLKs

5.4ns

2.0ns

125MHz(8ns)

3CLKs

6CLKs

9CLKs

3CLKs

6ns

2.0ns

100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

2.0ns

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

3CLKs

6CLKs

9CLKs

3CLKs

6ns

2.0ns

100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

2.0ns

83MHz(12ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

2.0ns

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

2.0ns

83MHz(12ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

2.0ns

66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

2.0ns

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

3CLKs

2CLKs

5CLKs

7CLKs

2CLKs

6ns

2.0ns

83MHz(12ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

2.0ns

66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

2.0ns

HY5V56B(L/S)F

Rev. 0.1/Oct. 02 13

COMMAND TRUTH TABLE

Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don

t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.

Command

CKEn-1

CKEn

RAS

CAS

DQM

ADDR

A10/

Note

Mode Register Set

OP code

No Operation

Bank Active

Read

Read with Autoprecharge

Write

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

DQM

Auto Refresh

Burst-Read-Single-
WRITE

A9 ball High

(Other balls OP code)

MRS

Mode

Self Refresh

Entry

Exit

Precharge
power down

Entry

Exit

Clock
Suspend

Entry

Exit

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HY5V56BF-S

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HY5V56BF-S