32Mx64 bits

Unbuffered DDR SO-DIMM

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Mar. 2003 1

HYMD232M646C(L)6-J/M/K/H/L

DESCRIPTION

Hynix HYMD232M646C(L)6-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix
HYMD232M646C(L)6-J/M/K/H/L series consists of eight 16Mx16 DDR SDRAM in 400mil TSOP II packages on a
200pin glass-epoxy substrate. Hynix HYMD232M646C(L)6-J/M/K/H/L series provide a high performance 8-byte inter-
face in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD232M646C(L)6-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD232M646C(L)6-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Factor

HYMD232M646C(L)6-J

=2.5V

DDQ

=2.5V

166MHz (*DDR333)

SSTL_2

200pin Unbuffered SO-DIMM

67.6mm x 31.75mm x 1mm

HYMD232M646C(L)6-M

133MHz (*DDR266:2-2-2)

HYMD232M646C(L)6-K

133MHz (*DDR266A)

HYMD232M646C(L)6-H

133MHz (*DDR266B)

HYMD232M646C(L)6-L

100MHz (*DDR200)

256MB (32M x 64) Unbuffered DDR SO-DIMM
based on 16Mx16 DDR SDRAM

JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2
interface

Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz

All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock

Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock

Data inputs on DQS centers when write (centered
DQ)

Data strobes synchronized with output data for read
and input data for write

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

* JEDEC Defined Specifications compliant

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

PIN DESCRIPTION

PIN ASSIGNMENT

Pin

Pin Description

Pin

Pin Description

CK0, /CK0, CK1, /CK1

Differential Clock Inputs

VDDQ

DQs Power Supply

CS0, CS1

Chip Select Input

VSS

Ground

CKE0, CKE1

Clock Enable Input

VREF

Reference Power Supply

/RAS, /CAS, /WE

Commend Sets Inputs

VDDSPD

Power Supply for SPD

A0 ~ A12

Address

SA0~SA2

PROM Address Inputs

BA0, BA1

Bank Address

SCL

PROM Clock

DQ0~DQ63

Data Inputs/Outputs

SDA

PROM Data I/O

DQS0~DQS7

Data Strobe Inputs/Outputs

VDDID

VDD Identification Flag

DM0~DM7

Data-in Mask

Do not Use

VDD

Power Supply

No Connection

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

VREF

VSS

101

102

151

DQ42

152

DQ46

VSS

DQ19

DQ23

103

VSS

104

VSS

153

DQ43

154

DQ47

DQ0

DQ4

DQ24

DQ28

105

106

155

VDD

156

VDD

DQ1

DQ5

VDD

107

108

157

VDD

158

/CK1

VDD

DQ25

DQ29

109

110

159

VSS

160

CK1

DQS0

DM0

DQS3

DM3

111

112

161

VSS

162

VSS

DQ2

DQ6

VSS

113

VDD

114

VDD

163

DQ48

164

DQ52

VSS

DQ26

DQ30

115

A10/AP

116

BA1

165

DQ49

166

DQ53

DQ3

DQ7

DQ27

DQ31

117

BA0

118

/RAS

167

VDD

168

VDD

DQ8

DQ12

VDD

119

/WE

120

/CAS

169

DQS6

170

DM6

VDD

121

/CS0

122

/CS1

171

DQ50

172

DQ54

DQ9

DQ13

123

124

173

VSS

174

VSS

DQS1

DM1

VSS

125

VSS

126

VSS

175

DQ51

176

DQ55

VSS

127

DQ32

128

DQ36

177

DQ56

178

DQ60

DQ10

DQ14

129

DQ33

130

DQ37

179

VDD

180

VDD

DQ11

DQ15

VDD

131

VDD

132

VDD

181

DQ57

182

DQ61

VDD

133

DQS4

134

DM4

183

DQS7

184

DM7

CK0

VDD

135

DQ34

136

DQ38

185

VSS

186

VSS

/CK0

VSS

137

VSS

138

VSS

187

DQ58

188

DQ62

VSS

139

DQ35

140

DQ39

189

DQ59

190

DQ63

DQ16

DQ20

VDD

141

DQ40

142

DQ44

191

VDD

192

VDD

DQ17

DQ21

VDD

143

VDD

144

VDD

193

SDA

194

SA0

VDD

CKE1

CKE0

145

DQ41

146

DQ45

195

SCL

196

SA1

DQS2

DM2

147

DQS5

148

DM5

197 VDDSPD 198

SA2

DQ18

DQ22

A12

100

A11

149

VSS

150

VSS

199

VDDID

200

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

FUNCTIONAL BLOCK DIAGRAM

/CS0

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

DQS0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM1

DQS1

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM2

DQS2

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM3

DQS3

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM4

DQS4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM5

DQS5

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM6

DQS6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM7

DQS7

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS1

BA0-BA1

SDRAMs D0 D7

A0 - A12

SDRAMs D0 D7

/RAS

SDRAMs D0 D7

/CAS

SDRAMs D0 D7

/WE

SDRAMs D0 D7

CKE0

SDRAMs D0 D3

CKE1 SDRAMz D4 - D7

VDDSPD

VREF

VSS

VDDID

SPD

D0 - D7

. .

Strap:see Note 4

VDD/VDDQ

Notes:

DQ wiring may differ from that described in this drawing ;

however DQ/DM/DQS relationship are maintained as shown.

VDDID strap connections;

(for memory device VDD, VDDQ) :

Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD= VDDQ

Serial PD

SCL
SA0
SA1
SA2

SDA

A0
A1
A2

/CS0

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

DQS0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM1

DQS1

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM2

DQS2

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM3

DQS3

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM4

DQS4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM5

DQS5

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM6

DQS6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM7

DQS7

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS1
/CS0

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

DQS0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM1

DQS1

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

DQS0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM1

DQS1

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM2

DQS2

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM3

DQS3

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM4

DQS4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM5

DQS5

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM4

DQS4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM5

DQS5

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM6

DQS6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM7

DQS7

/CS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

/CS1

BA0-BA1

SDRAMs D0 D7

A0 - A12

SDRAMs D0 D7

/RAS

SDRAMs D0 D7

/CAS

SDRAMs D0 D7

/WE

SDRAMs D0 D7

CKE0

SDRAMs D0 D3

CKE1 SDRAMz D4 - D7

BA0-BA1

SDRAMs D0 D7

A0 - A12

SDRAMs D0 D7

/RAS

SDRAMs D0 D7

/CAS

SDRAMs D0 D7

/WE

SDRAMs D0 D7

CKE0

SDRAMs D0 D3

CKE1 SDRAMz D4 - D7

VDDSPD

VREF

VSS

VDDID

SPD

D0 - D7

. .

Strap:see Note 4

VDD/VDDQ

VDDSPD

VREF

VSS

VDDID

SPD

D0 - D7

. .

Strap:see Note 4

VDD/VDDQ

Notes:

DQ wiring may differ from that described in this drawing ;

however DQ/DM/DQS relationship are maintained as shown.

VDDID strap connections;

(for memory device VDD, VDDQ) :

Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD= VDDQ

Serial PD

SCL
SA0
SA1
SA2

SDA

A0
A1
A2

Serial PD

SCL
SA0
SA1
SA2

SDA

A0
A1
A2

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :
1. V

DDQ

must not exceed the level of V

2. V

(min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. The value of V

REF

is approximately equal to 0.5V

DDQ

AC OPERATING CONDITIONS

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

Storage Temperature

STG

-55 ~ 125

Voltage on Any Pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

relative to V

-0.5 ~ 3.6

Voltage on V

DDQ

relative to V

DDQ

-0.5 ~ 3.6

Output Short Circuit Current

Power Dissipation

Soldering Temperature Þ Time

SOLDER

260 / 10

C / Sec

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

2.3

2.5

2.7

Power Supply Voltage

DDQ

2.3

2.5

2.7

Input High Voltage

REF

+ 0.15

DDQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

Termination Voltage

REF

- 0.04

REF

+ 0.04

Reference Voltage

REF

0.49*VDDQ

0.5*VDDQ

0.51*VDDQ

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

IH(AC)

REF

+ 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

IL(AC)

REF

- 0.31

Input Differential Voltage, CK and /CK inputs

ID(AC)

0.7

DDQ

+ 0.6

Input Crossing Point Voltage, CK and /CK inputs

IX(AC)

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

DC CHARACTERISTICS II

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Parameter

Symbol

Test Condition

Speed

Unit Note

-J

-M

-K

-H

-L

Operating Current

IDD0

One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
control inputs changing once per clock cycle

660

580

560

Operating Current

IDD1

One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle

840

720

680

Precharge Power
Down Standby Current

IDD2P

All banks idle; Power down - mode; CKE=Low,
tCK=tCK(min)

160

Idle Standby Current

IDD2F

/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and
DM

400

320

280

Active Power Down
Standby Current

IDD3P

One bank active; Power down mode; CKE=Low,
tCK=tCK(min)

200

Idle Quiet Standby
Current

DD2Q

/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable,
Vin=Vref for DQ, DQS and DM

TBD

Active Standby
Current

IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle

480

400

Operating Current

IDD4R

Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); IOUT=0mA

1400 1400 1200 1200

960

Operating Current

IDD4W

Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM,
and DQS inputs changing twice per clock cycle

1400 1400 1200 1200

960

Auto Refresh Current

IDD5

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh

1160 1160 1040 1040

980

Self Refresh Current

IDD6

CKE=<0.2V; External clock on;
tCK =tCK(min)

Normal

Low Power

Operating Current -
Four Bank Operation

IDD7

Four bank interleaving with BL=4 Refer to the
following page for detailed test condition

1580 1580 1500 1500 1360

Random Read Current

DD7A

4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS
inputs changing twice per clock cycle; 100%
addresses changing once per clock cycle

TBD

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

<DDR333, DDR266(2-2-2)>

Parameter

Symbol

DDR333

DDR266(2-2-2)

Unit

Note

Min

Max

Min

Max

Row Cycle Time

Auto Refresh Row Cycle Time

RFC

Row Active Time

RAS

70K

120K

Active to Read with Auto Precharge Delay

RAP

Row Address to Column Address Delay

RCD

Row Active to Row Active Delay

RRD

Column Address to Column Address Delay

CCD

Row Precharge Time

Write Recovery Time

tWR

Write to Read Command Delay

WTR

Auto Precharge Write Recovery + Precharge Time

DAL

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

System Clock Cycle Time

CL = 2.5

7.5

CL = 2

7.5

Clock High Level Width

0.45

0.55

0.45

0.55

Clock Low Level Width

0.45

0.55

0.45

0.55

Data-Out edge to Clock edge Skew

-0.7

0.7

-0.75

0.75

DQS-Out edge to Clock edge Skew

DQSCK

-0.6

0.6

-0.75

0.75

DQS-Out edge to Data-Out edge Skew

DQSQ

0.45

0.5

Data-Out hold time from DQS

-t

QHS

-t

QHS

1, 10

Clock Half Period

min

(tCL,tCH)

min

(tCL,tCH)

1,9

Data Hold Skew Factor

QHS

0.55

0.75

Valid Data Output Window

-t

DQSQ

-t

DQSQ

Data-out high-impedance window from CK, /CK

-0.7

0.7

-0.75

0.75

Data-out low-impedance window from CK, /CK

-0.7

0.7

-0.75

0.75

Input Setup Time (fast slew rate)

0.75

0.9

2,3,5,6

Input Hold Time (fast slew rate)

0.75

0.9

2,3,5,6

Input Setup Time (slow slew rate)

0.8

1.0

2,4,5,6

Input Hold Time (slow slew rate)

0.8

1.0

2,4,5,6

Input Pulse Width

IPW

2.2

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

<DDR266A/B, DDR200>

Parameter

Symbol

DDR266A

DDR266B

DDR200

Unit

Note

Min

Max

Min

Max

Min

Max

Row Cycle Time

Auto Refresh Row Cycle Time

RFC

Row Active Time

RAS

120K

120k

Active to Read with Auto Precharge Delay

RAP

Row Address to Column Address Delay

RCD

Row Active to Row Active Delay

RRD

Column Address to Column Address Delay

CCD

Row Precharge Time

Write Recovery Time

tWR

Write to Read Command Delay

WTR

Auto Precharge Write Recovery +
Precharge Time

DAL

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

System Clock Cycle
Time

CL = 2.5

7.5

8.0

CL = 2

7.5

Clock High Level Width

0.45

0.55

0.45

0.55

0.45

0.55

Clock Low Level Width

0.45

0.55

0.45

0.55

0.45

0.55

Data-Out edge to Clock edge Skew

-0.75

0.75

-0.75

0.75

-0.8

0.8

DQS-Out edge to Clock edge Skew

DQSCK

-0.75

0.75

-0.75

0.75

-0.8

0.8

DQS-Out edge to Data-Out edge Skew

DQSQ

0.5

0.6

Data-Out hold time from DQS

-t

QHS

-t

QHS

-t

QHS

1, 10

Clock Half Period

min

(tCL,tCH)

min

(tCL,tCH)

min

(tCL,tCH)

1,9

Data Hold Skew Factor

QHS

0.75

Valid Data Output Window

-t

DQSQ

-t

DQSQ

-t

DQSQ

Data-out high-impedance window from
CK, /CK

-0.75

0.75

-0.75

0.75

-0.8

0.8

Data-out low-impedance window from
CK, /CK

-0.75

0.75

-0.75

0.75

-0.8

0.8

Input Setup Time (fast slew rate)

0.9

1.1

2,3,5,6

Input Hold Time (fast slew rate)

0.9

1.1

2,3,5,6

Input Setup Time (slow slew rate)

1.0

1.1

2,4,5,6

Input Hold Time (slow slew rate)

1.0

1.1

2,4,5,6

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

Note :

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

For command/address input slew rate >=1.0V/ns

For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.

5. CK, /CK slew rates are >=1.0V/ns

6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.

This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

Input Setup / Hold Slew-rate

Delta tIS

Delta tIH

V/ns

0.5

0.4

+50

0.3

+100

Input Setup / Hold Slew-rate

Delta tDS

Delta tDH

V/ns

0.5

0.4

+75

0.3

+150

I/O Input Level

Delta tDS

Delta tDH

+280

+50

(1/SlewRate1)-(1/SlewRate2)

Delta tDS

Delta tDH

ns/V

+/-0.25

+50

+/- 0.5

+100

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

SIMPLIFIED COMMAND TRUTH TABLE

Note :
1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A

and BA

~BA

used for Mode Registering duing Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+t

4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+t

DPL

). Last Data-In to Prechage delay(t

DPL

) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.
5. If A

/AP is High when Row Precharge command being issued, BA

/BA

are ignored and all banks are selected to be

precharged.

Command

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

ADDR

A10/

Note

Extended Mode Register Set

OP code

1,2

Mode Register Set

OP code

1,2

Device Deselect

No Operation

Bank Active

Read

Read with Autoprecharge

1,3

Write

Write with Autoprecharge

1,4

Precharge All Banks

1,5

Precharge selected Bank

Read Burst Stop

Auto Refresh

Self Refresh

Entry

Exit

Precharge
Power Down
Mode

Entry

Exit

Active Power
Down Mode
(Clock Suspend)

Entry

Exit

( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

SERIAL PRESENCE DETECT

Byte#

Function Description

Function Supported

Hexa Value

Note

Number of Bytes written into serial memory at module
manufacturer

128 Bytes

80h

Total number of Bytes in SPD device

256 Bytes

08h

Fundamental memory type

DDR SDRAM

07h

Number of row address on this assembly

0Dh

Number of column address on this assembly

09h

Number of physical banks on DIMM

2Bank

02h

Module data width

64 Bits

40h

Module data width (continued)

00h

Module voltage Interface levels(VDDQ)

SSTL 2.5V

04h

DDR SDRAM cycle time at CAS Latency=2.5(tCK)

6.0ns

7.5ns

7.5ns 7.5ns

8.0ns

60h

75h

80h

DDR SDRAM access time from clock at CL=2.5 (tAC)

+/-0.7ns

+/-0.75ns

+/-0.8ns 70h

75h

80h

Module configuration type

Non-ECC

00h

Refresh rate and type

7.8us & Self refresh

82h

Primary DDR SDRAM width

x16

10h

Error checking DDR SDRAM data width

N/A

00h

Minimum clock delay for back-to-back random column
address(tCCD)

1 CLK

01h

Burst lengths supported

2,4,8

0Eh

Number of banks on each DDR SDRAM

4 Banks

04h

CAS latency supported

2, 2.5

0Ch

CS latency

01h

WE latency

02h

DDR SDRAM module attributes

Differential Clock Input

20h

DDR SDRAM device attributes : General

+/-0.2Voltage tolerance,

Concurrent Auto Precharge

tRAS Lock Out

C0h

DDR SDRAM cycle time at CL=2.0(tCK)

7.5ns

10ns

75h

A0h

DDR SDRAM access time from clock at CL=2.0(tAC)

+/-0.7ns

+/-0.75ns

+/-0.8ns 70h

75h

80h

DDR SDRAM cycle time at CL=1.5(tCK)

00h

DDR SDRAM access time from clock at CL=1.5(tAC)

00h

Minimum row precharge time(tRP)

18ns

15ns

20ns

48h

3Ch

50h

Minimum row activate to row active delay(tRRD)

12ns

15ns

30h

3Ch

Minimum RAS to CAS delay(tRCD)

18ns

15ns

20ns

48h

3Ch

50h

Minimum active to precharge time(tRAS)

42ns

45ns

50ns

2Ah

2Dh

32h

Module row density

128MB

20h

Command and address signal input setup time(tIS)

0.75ns

0.9ns

0.9ns 0.9ns

1.1ns

75h

90h

B0h

Command and address signal input hold time(tIH)

0.75ns

0.9ns

0.9ns 0.9ns

1.1ns

75h

90h

B0h

Data signal input setup time(tDS)

0.45ns

0.5ns

0.5ns 0.5ns

0.6ns

45h

50h

60h

Data signal input hold time(tDH)

0.45ns

0.5ns

0.5ns 0.5ns

0.6ns

45h

50h

60h

36~40 Reserved for VCSDRAM

Undefined

00h

Minimum active / auto-refresh time ( tRC)

60ns

65ns

70ns

3Ch

41h

46h

Minimum auto-refresh to active/auto-refresh
command period(tRFC)

72ns

75ns

80ns

48h

4Bh

50h

Maximum cycle time (tCK max)

12ns

30h

Maximim DQS-DQ skew time(tDQSQ)

0.45ns

0.5ns

0.5ns 0.5ns

0.6ns

2Dh

32h

3Ch

Maximum read data hold skew factor(tQHS)

0.55ns

0.75ns

0.75n

0.75ns

55h

75h

46~61 Superset information(may be used in future)

Undefined

00h

SPD Revision code

Initial release

00h

Checksum for Bytes 0~62

E8h

72h

9Fh

CAh

64h

Bin Sort :J(DDR333),M(DDR266(2-2-2)),K(DDR266A@CL=2)

H(DDR266B@CL=2.5),L(DDR200@CL=2)

HYMD232M646C(L)6-J/M/K/H/L

Rev. 0.1 / Mar. 2003

SERIAL PRESENCE DETECT

- continued -

Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix's own Module Serial Number system
5. These bytes undefined and coded as `00h'
6. Refer to Hynix web site

Byte 85~86, Low power part

Byte #

Function Description

Function Supported

Hexa Value

Note

Manufacturer JEDEC ID Code

Hynix JEDEC ID

ADh

65~71

--------- Manufacturer JEDEC ID Code

00h

Manufacturing location

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

Asia Area

0*h
1*h
2*h
3*h
4*h
5*h

Manufacture part number(Hynix Memory Module)

48h

-------- Manufacture part number(Hynix Memory Module)

59h

-------- Manufacture part number(Hynix Memory Module)

4Dh

Manufacture part number (DDR SDRAM)

44h

Manufacture part number(Memory density)

32h

Manufacture part number(Module Depth)

33h

------- Manufacture part number(Module Depth)

32h

Manufacture part number(Module type)

4Dh

Manufacture part number(Data width)

36h

-------Manufacture part number(Data width)

34h

Manufacture part number(Refresh, # of Bank.)

6(8K refresh,4Bank)

36h

Manufacture part number(Component Generation)

43h

Manufacture part number(Component configuration)

36h

Manufacture part number(Hyphen)

`-'

2Dh

Manufacture part number(Minimum cycle time)

4Ah

4Dh

4Bh

48h

4Ch

88~90

Manufacture part number(T.B.D)

Blank

20h

Manufacture revision code(for Component)

Manufacture revision code (for PCB)

Manufacturing date(Year)

Manufacturing date(Week)

95~98

Module serial number

99~127

Manufacturer specific data (may be used in future)

Undefined

00h

128~255 Open for customer use

Undefined

00h

Byte #

Function Description

Function Supported

Hexa Value

Note

Manufacture part number(Low power part)

4Ch

Manufacture part number(Component configuration)

36h

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