Standard cell/gate array ASIC for high-function,
high-density applications
Blue Logic Cu-11 ASIC
Highlights
0.11-m L drawn enables designs
of up to 40 million gates
Advanced technologies include
copper metallurgy and low-k
dielectric
Choice of packaging options
such as electrically superior
HyperBGA
IBM Blue LogicTM design
methodology supports seamless
integration and enables first-
time-right design
Extensive portfolio of cores
provides time-to-market
advantage
Integration and performance
geared to the most demanding
applications
The IBM Blue Logic Cu-11 ASIC is IBM's
most advanced ASIC design system,
achieving new levels of integration and
performance to satisfy today's demand-
ing application requirements. A high-
density standard cell and gate array
ASIC, the Cu-11 capitalizes on IBM's
advanced semiconductor process,
including its pioneering copper technol-
ogy, low-k dielectric and effective
channel length of 0.08 m, to achieve a
density of up to 40 million gates and
performance featuring 27-ps gate delay.
Additionally, the Cu-11 ASIC's embedded
DRAM, dense SRAM and dual library
Section showing Cu-11 copper and low-k
dielectric process.
options are optimized for significantly
improved density and performance.
These leadership features make the
Cu-11 ASIC an ideal solution for commu-
nications, data processing and consumer
applications, including GSM base stations,
routers, processor chipsets and server
I/O functions. Further, the exceptional
capabilities of the Cu-11 ASIC allow
customers to replace several ASICs with
one Cu-11 ASIC design. High integration
saves space, power, and the delay and
noise associated with bussing signals
across a board.
The newest offering within the IBM Blue
Logic ASIC program, the Cu-11 ASIC
demonstrates IBM's ongoing commit-
ment to technology leadership and
customer satisfaction. To help customers
improve time-to-market, dozens of cores
from the IBM Blue Logic core portfolio
have been optimized and migrated to
the Cu-11 design system, providing pre-
verified building blocks for rapid design.
Product Specifications
L
eff
= 0.08 m, L drawn = 0.11 m
Up to 40 million wireable gates
Trench capacitor embedded DRAM with
up to 16 Mb per macro
Dense high-performance, compilable
SRAMs
Power supply: 1.2 V with 1.5 V option
I/O power supply: 3.3 V(dual oxide option)/
2.5 V(dual oxide option)/1.8 V/1.5 V
Power dissipation of 0.009 W/MHz/gate
Gate delays of 27 picoseconds (2-input
NAND gate)
Seven levels of copper for global routing
Low-k dielectric for high performance
and reduced power and noise
Automatic gate array fill of free space for
quick-turn engineering change options
Two logic library options for performance
and density advantage
Packaging options, including laminate,
ceramic, plastic ball grid arrays, and
plastic quad flat packs
Embedded DRAM supports faster
data transfers
Elegantly integrated into the chip, Cu-11
embedded DRAM features a leading-
edge performance of 15-nsec random
cycle time and a density of 2.09 mm
2
for
1-Mb core size. These exceptional char-
acteristics, combined with Cu-11 interface
flexibility and self-testability, bring the
advantages of wider bandwidth, reduced
pin counts, and faster data transfers to
Cu-11 ASIC-based designs.
IBM Blue Logic core program
enables seamless and efficient
design
The IBM Blue Logic Cu-11 core program,
which builds on proven Blue Logic
technology, combines industry-standard
intellectual property (IP) with IBM
proprietary IP to solve integration issues
and make application design seamless
and efficient. With Blue Logic cores,
function and timing parameters are
resolved. In addition, IBM's system-level-
silicon design methodology supports
these cores, helping manufacturers meet
design parameters.
Dozens of Cu-11 cores, such as proces-
sors featuring the performance advan-
tage of the IBM PowerPC
architecture
and industry-standard ARM processors,
are included in IBM's portfolio of over
200 IBM Blue Logic cores. The portfolio
incorporates cores that focus on the
need for speed in clocking, data transfer,
standard inter facing, and connectivity.
It also includes cores that serve data
processing, communications, and con-
sumer applications, focusing in areas
such as local and wide area networks,
data transfer and 3D graphics. The IBM
CoreConnectTM bus architecture eases
the integration and reuse of these
processor, system and peripheral cores
in IBM Cu-11 system-on-a-chip designs.
Tools, methodology and expert
services that help deliver
working silicon, on time
IBM offers a proven methodology, robust
tools and design services to help
customers reduce product development
time. IBM supports many industry-
standard CAD tools and offers IBM
design tools incorporating advanced
features that enable seamless inclusion
of a choice of cores for system-level-
silicon. The IBM Blue Logic methodology
includes the ASIC sign-off toolkit, a clock
distribution methodology, floor-planning,
timing analysis, and automatic test pattern
generation. In addition, an enhanced
placement-driven synthesis methodology is
available with Cu-11 to help customers
achieve aggressive performance targets
and reduce turn-around-time. In support of
these tools and methodologies, IBM's
worldwide design centers offer customized
services, including one-on-one design
consultation, documentation, and focused
education in tools and methodology.
Packaging
HyperBGA (flip chip): 2577 total leads*
CCGA (flip chip): 1657 total leads (with
extension of up to 2577*)
CBGA (flip chip): 937 total leads
PBGA (flip chip): 1680 total leads*
PBGA/E-PBGA/HPBGA (wire bond):
580 total leads
LQFP, PQFP, and TQFP: 240 total leads
TFBGA: 220 total leads
Library Elements
Two complete library offerings are available
with Cu-11: a performance optimization
base library and a library for density
optimization. Each offers a comprehensive
set of library elements in multiple drive
strengths and includes scannable D flip-
flops for automatic test-pattern generation.
IBM offers the following input/
output library elements:
CMOS, LVTTL, SSTL2, PCI-X, HSTL, LVDS
ESD protection
3.0 k V
For more information, visit our Web site at
www.chips.ibm.com.
*
Package in development. Lead count is estimated.
Embedded Memory and Macros
Function
Capability
Embedded DRAM
1 Mb to 16 Mb in 1 Mb increments, Multiple macros
per chip, Cell size: 0.31 m
2
, 14.1 mm
2
for 16 Mb
Macro, Trench capacitor, Built-In Self Test
Compilable 1-Port SRAM
Maximum Size: 1M bits, Maximum words: 32768
Maximum width: 128 bits, Multiple Array Built-in Self Test
Low Power Compilable 1-Port SRAM
Maximum Size: 256K bits, Maximum words: 16384
Maximum width: 36 bits, Multiple Array Built-in Self Test
Compilable 2-Port SRAM
Maximum Size: 128K bits, Maximum words: 4096
Maximum width: 128 bits, Multiple Array Built-in Self Test
Compilable Dual-Port SRAM
Maximum Size: 256K bits, Maximum words: 8192
Maximum width: 128 bits, Multiple Array Built-in Self Test
Compilable ROM
Maximum Size: 1M bits, Maximum words: 32768
Maximum width: 64 bits, Array Built-in Self Test
Compilable Register Arrays
2-Port, 3-Port, 4-Port
SA14-2451-00
*07SA14245100*
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