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prs64G.03title.fm
July 2, 2002

IBM PowerPRS 64G

Packet Routing Switch

prs64G.03TOC.fm
July 2, 2002

Contents

Page 3 of 159

Contents

List of Figures ................................................................................................................. 7

List of Tables ................................................................................................................... 9

1. General Information .................................................................................................. 11

1.1 Features ......................................................................................................................................... 11
1.2 Description .................................................................................................................................... 11
1.3 Ordering Information .................................................................................................................... 12
1.4 Conventions and Notation ........................................................................................................... 12

2. Architecture ............................................................................................................... 13

2.1 System Application ....................................................................................................................... 13
2.2 Internal Structure .......................................................................................................................... 14

2.2.1 DASL Interface ...................................................................................................................... 15
2.2.2 Shared Memory ..................................................................................................................... 15
2.2.3 Sequencer ............................................................................................................................. 16
2.2.4 Address Manager .................................................................................................................. 16
2.2.5 Input Controllers .................................................................................................................... 16
2.2.6 Output Queue Access Manager ............................................................................................ 16
2.2.7 Output Queues ...................................................................................................................... 17
2.2.8 Output Queue Read Manager and Credit Table .................................................................... 17
2.2.9 Output Controllers ................................................................................................................. 17

2.3 Speed Expansion Configurations ................................................................................................ 17

2.3.1 Basic Configuration: One Device without Speed Expansion ................................................. 17
2.3.2 One Device with Internal Speed Expansion .......................................................................... 18
2.3.3 Two Devices with External Speed Expansion ....................................................................... 18
2.3.4 Two Devices with Internal and External Speed Expansion ................................................... 19
2.3.5 Speed Expansion Summary .................................................................................................. 20

2.4 Port Expansion .............................................................................................................................. 21
2.5 Port Paralleling .............................................................................................................................. 21

3. Functional Description ............................................................................................. 23

3.1 Packet Type ................................................................................................................................... 23

3.1.1 Data Packets ......................................................................................................................... 23
3.1.2 Control Packets ..................................................................................................................... 23
3.1.3 Idle Packets ........................................................................................................................... 24
3.1.4 Synchronization Packets ....................................................................................................... 24
3.1.5 Service Packets ..................................................................................................................... 24

3.2 Physical Interface .......................................................................................................................... 24
3.3 Logical Unit Format versus Speed Expansion Configuration .................................................. 25

3.3.1 Basic Configuration: One Device without Speed Expansion ................................................. 26
3.3.2 One Device with Internal Speed Expansion or Two Devices with External Speed Expansion .. 26
3.3.3 Two Devices with Internal and External Speed Expansion ................................................... 27
3.3.4 Two Devices with Port Paralleling and External Speed Expansion ....................................... 27
3.3.5 Master/Slave Synchronization with Two Devices .................................................................. 27

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Packet Routing Switch

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3.4 Packet Format According to Packet Type .................................................................................. 29

3.4.1 Packet Signaling .................................................................................................................... 29
3.4.2 Data/Control Packet Format .................................................................................................. 29
3.4.3 Idle Packet Format ................................................................................................................. 33
3.4.4 Synchronization Packet Format ............................................................................................. 35
3.4.5 Service Packet Format ........................................................................................................... 36

3.5 Ingress Flow Control ..................................................................................................................... 36

3.5.1 Output Queue Grants ............................................................................................................. 37
3.5.2 Memory Grants ..................................................................................................................... 37
3.5.3 Shared Memory Overrun ....................................................................................................... 38
3.5.4 Receive Grants ...................................................................................................................... 38
3.5.5 Flow Control Latency ............................................................................................................. 38
3.5.6 Best-Effort Discard ................................................................................................................. 38

3.6 Egress Flow Control ..................................................................................................................... 41

3.6.1 Send Grants ........................................................................................................................... 41
3.6.2 Send Grant Antistreaming ...................................................................................................... 42
3.6.3 Credit Table ........................................................................................................................... 42

3.7 Packet Reception .......................................................................................................................... 43

3.7.1 Idle Packet Reception ............................................................................................................ 43
3.7.2 Data Packet Reception .......................................................................................................... 43
3.7.3 Control Packet Reception ...................................................................................................... 44
3.7.4 Reading an Ingress Control Packet ....................................................................................... 45

3.8 Packet Transmission .................................................................................................................... 46

3.8.1 Output Port Servicing ............................................................................................................. 46
3.8.2 Look-Up Tables ...................................................................................................................... 46
3.8.3 Control Packet Transmission ................................................................................................. 47
3.8.4 Idle Packet Transmission ....................................................................................................... 48
3.8.5 Service Packet Transmission ................................................................................................. 49

3.9 Side Communication Channel ..................................................................................................... 49
3.10 Switchover Support .................................................................................................................... 49

3.10.1 Switchover Mechanism ........................................................................................................ 49
3.10.2 Scheduled Switchover Process ........................................................................................... 51

3.11 Port Paralleling ............................................................................................................................ 53

3.11.1 Packet Processing with Port Paralleling .............................................................................. 53
3.11.2 Bitmap Mapping with Port Paralleling .................................................................................. 53

4. Programming Interface ............................................................................................. 57

4.1 SHI Instruction Register ............................................................................................................... 57
4.2 SHI Instruction Execution ............................................................................................................. 58
4.3 SHI Parity Checking ...................................................................................................................... 58
4.4 SHI Parity Generation ................................................................................................................... 58
4.5 Status Register .............................................................................................................................. 59

5. Register Descriptions ............................................................................................... 61

5.1 SHI Internal Registers ................................................................................................................... 63

5.1.1 PLL Programming Register .................................................................................................... 63
5.1.2 Reset Register ....................................................................................................................... 64
5.1.3 Interrupt Mask Register .......................................................................................................... 65
5.1.4 BIST Counter Register ........................................................................................................... 66

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Packet Routing Switch

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5.1.5 BIST Data Register ................................................................................................................ 67
5.1.6 BIST Select Register ............................................................................................................. 68
5.1.7 Debug Bus Select Register ................................................................................................... 69

5.2 DASL Programming Registers ..................................................................................................... 72

5.2.1 DASL Output Driver Enable Register .................................................................................... 72
5.2.2 Output Port Enable Register .................................................................................................. 72
5.2.3 Synchronization Packet Transmit Register ............................................................................ 73
5.2.4 Input Port Enable Register .................................................................................................... 73
5.2.5 DASL Signal Lost Register .................................................................................................... 74
5.2.6 SDC RLOS Enable Register .................................................................................................. 74
5.2.7 DASL Synchronization Hunt Register .................................................................................... 75
5.2.8 DASL Synchronization Status Register ................................................................................. 75
5.2.9 Picoprocessor Instruction Memory Access Register ............................................................. 76
5.2.10 DASL Configuration Register .............................................................................................. 77
5.2.11 DASL Port Error Register .................................................................................................... 78
5.2.12 DASL Port Quality Mask Register ....................................................................................... 78
5.2.13 DASL Port Quality Register ................................................................................................. 78
5.2.14 SDC Resource Address Registers ...................................................................................... 79
5.2.15 SDC Resource Control Registers ........................................................................................ 80
5.2.16 SDC Resource Data Registers ............................................................................................ 81
5.2.17 SDC Status Registers .......................................................................................................... 82

5.3 Flow Control Pin Status and Setting Registers .......................................................................... 83

5.3.1 Send Grant per Priority Register ........................................................................................... 83
5.3.2 Send Grant Status Register ................................................................................................... 83
5.3.3 Receive Grant Status Register .............................................................................................. 84

5.4 Functional Registers ..................................................................................................................... 85

5.4.1 Configuration 0 Register ........................................................................................................ 85
5.4.2 Configuration 1 Register ........................................................................................................ 87
5.4.3 Output Queue Enable Register ............................................................................................. 89
5.4.4 Input Controller Enable Register ........................................................................................... 90
5.4.5 Color Detection Disable Register .......................................................................................... 90
5.4.6 Send Grant Enable Register .................................................................................................. 91
5.4.7 Force Send Grant Register .................................................................................................... 91
5.4.8 Expected Color Received Register ........................................................................................ 92
5.4.9 CRC Error Register ............................................................................................................... 92
5.4.10 Header Parity Error Register ............................................................................................... 93
5.4.11 Error Counter Register ........................................................................................................ 93
5.4.12 Flow Control Violation Register ........................................................................................... 94
5.4.13 Control Packet Counter Register ......................................................................................... 94
5.4.14 Output Queue Status Registers ........................................................................................... 95
5.4.15 Color Packet Received Register .......................................................................................... 96
5.4.16 Send Grant Violation Register ............................................................................................. 97
5.4.17 Occupancy Counter Register .............................................................................................. 97
5.4.18 Shared Memory Access Registers ...................................................................................... 98
5.4.19 Shared Memory Pointer Register ........................................................................................ 99
5.4.20 Shared Memory Data Register ............................................................................................ 99
5.4.21 Command Register ............................................................................................................ 100
5.4.22 Control Packet Destination Register .................................................................................. 101
5.4.23 Bitmap Filter Register ........................................................................................................ 101
5.4.24 Threshold Access Register ................................................................................................ 102

Электронный компонент: PRS64G

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