iC-JRX

µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

Rev A1, Page 1/23

PLCC44

VB -5.8V

IO0

IL0

IL1

IL0

Toff1

Toff2

3.8V

D3
D4
D5
D6
D7

A0
A1
A2
A3
A4

D0
D1
D2

E/A LOGIK

iC-JRX

E/A LOGIK

RESN

GNDD

RDN

WRN

CSN

VCCD

VCCA

NIOL

IO0

SC0

PSEL0

PEN0

OUT0

INTN

BLFQ

CLK

TEST

POE

GNDA

PGND

IO7

IO6

IO5

VB67

IO4

VB45

IO3

IO2

IO1

VB23

IO0

VB01

EIN-/AUSGANG STUFE 0

EIN-/AUSGANG STUFE 1

EIN-/AUSGANG STUFE 2

EIN-/AUSGANG STUFE 3

EIN-/AUSGANG STUFE 4

EIN-/AUSGANG STUFE 5

EIN-/AUSGANG STUFE 6

EIN-/AUSGANG STUFE 7

NIOL

PSEL0

SC0

OUT

POE

NTC

0µA

200µA

0µA

200µA

600µA

2.0mA

IH1

IH0

NIOH

1
2
3

39
40
41
42
43

36
10
35
11
12

UNTERSPANNUNGS-

ERKENNUNG VCCA

FEATURES

APPLICATIONS

2 × 4 bidirectional input/output stages at 24 V

Input/output mode programmable in 4-bit blocks

Guaranteed high-side driving capability of 100 mA

and

500 mA

peak

for pulse load

Short-circuit-proof drivers with high dielectric strength

Low saturation voltage of 0.6 V at 100 mA and 2 V at 500 mA

Integrated flyback circuits

PWM function with programmable duty cycle

Flash mode for the outputs

Power outputs can be disabled together

Programmable current sources define logic levels and allow
load monitoring

Digital input filters with externally adjustable filtering times

Can be bus operated due to the high-speed µP interface

Programmable interrupt output

Voltage and two-stage temperature monitoring

Dual quad high-side driver as a
bidirectional µP interface with
digital filtering in industrial 24 V
applications

PACKAGES

BLOCK DIAGRAM

www.ichaus.com

iC-JRX

µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

Rev A1, Page 2/23

LA2

LA3

REL1

µP

LA1

D0..D7

A0..A7

ADRESS-

DEKODIERER

RESET

CONTROLLER

RES

INT

VB45

VB67

VCCA

VCCD

WRN

IO4

IO5

IO6

IO7

PGND

RDN

RESN

VB01

VB23

GNDA

GNDD

INTN

IO0

IO1

IO2

IO3

BLFQ

CLK

CSN

5 V

24 V

5 V

24 V

HIGHER
NIBBLE

NIBBLE

KONTROLL-

LOWER

PLCC44

iC-JRX

1.25 MHz

100 nF

TEST

POE

C3 100 nF

C4 100 nF

C5 100 nF

C6 100 nF

C2
3.3 ... 10 uF

DESCRIPTION

iC-JRX is an 8-fold high-side driver with integrated control logic, internally divided into two independent blocks
(nibbles). Both blocks can be individually set to input or output. The µP interface is made up of eight data, five
address and three control pins. Two further clock inputs control internal sequences (input filter, pulse
operation of the outputs). Starting with reset state, various register partitionings dependent on the selected
operating mode are possible.

Input mode is used to log logic levels at 24 V. An interrupt message can be generated when a signal at the
inputs changes. Spurious signals are rejected by the device's adjustable digital filters. When the inputs are
open the programmable pull-down current sets defined levels and acts as the bias current for switching
contacts.

In output mode the power output stages can drive any desired load to GND (e.g. lamps, long cables or relays)
at a continuous current of 100 mA or 500 mA in pulse operation. Spikes and flyback currents are discharged
through the integrated flyback circuits. All output stages are short-circuit-proof and two-stage temperature
monitoring (with interrupt messages) protects against thermal damage caused by large power dissipation. A
short circuit at one of the outputs can cause an interrupt; the current short circuit status can be scanned via
the µP interface. Pulse mode can be selected for each output, such as for indicator lamps in plugboards, in
order to offload the control software used. The actual switching level of the output can be read out via the µP
interface and be used to check for cable fractures with the pull-up currents. A PWM signal can also be
switched to any selected output. All outputs can be switched off via a mutual disable input e.g. by a processor-
independent watchdog circuit.

An interrupt pipeline which prevents the loss of interrupts allows reliable processing of interrupts using the
applied control software.

With low voltage the voltage monitor resets all registers and in doing so switches off the power output stages.

Diodes protect all inputs and outputs against ESD. The device is also immune to burst transients according
to IEC 1000-4-4 (4 kV; previously IEC 801-4).

Typical application circuit

iC-JRX

µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

Rev A1, Page 3/23

PACKAGES PLCC44 to JEDEC Standard

PIN CONFIGURATION PLCC44
(top view)

PIN FUNCTIONS PLCC44

No. Name

Fct.

Description No. Name

Fct.

Description

CSN

Chip Select, active low

PGND

Ground (ESD protection circuitry)

WRN

Write Enable, active low

IO3

I/O Stage 3

RDN

Read Enable, active low

VB23

Power Supply Driver Stage 2+3

BLFQ

Clock Flash Mode

IO2

I/O Stage 2

CLK

Clock Filter and PWM Function

IO1

I/O Stage 1

INTN

Interrupt Message, active low

VB01

Power Supply Driver Stage 0+1

RESN

Reset, active low

IO0

I/O Stage 0

Data Bus Bit 1

VCCA

+5 V Supply Voltage (analog section)

Data Bus Bit 3

POE

Power Output Enable

Data Bus Bit 5

n.c.

Data Bus Bit 7

n.c.

GNDD

Ground (digital section)

VCCD

+5 V Supply Voltage (digital section)

n.c.

Data Bus Bit 6

n.c.

Data Bus Bit 4

TEST

Test Pin

Data Bus Bit 2

GNDA

Ground (analog section)

Data Bus Bit 0

IO7

I/O Stage 7

Address Bus Bit 0

VB67

Power Supply Driver Stage 6+7

Address Bus Bit 1

IO6

I/O Stage 6

Address Bus Bit 2

IO5

I/O Stage 5

Address Bus Bit 3

VB45

Power Supply Driver Stage 4+5

Address Bus Bit 4

IO4

I/O Stage 4

n.c.

Functions: I = Input, O = Output, B = bidirectional
External wiring VCCA, VCCD to +5 V and GNDA, GNDD, PGND to 0 V required.

iC-JRX

µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

Rev A1, Page 4/23

PROGRAMMING

Register Overview

Address

A(4..0)d A4 A3 A2 A1 A0 Write

Read

Input Register

Change-of-input Message

Interrupt Status Register

Overcurrent Message

Overcurrent Status

Device ID

Output Register

Flash Pulse Enable

Change-of-input Interrupt Enable

Overcurrent Interrupt Enable

Control Word 1 (I/O filters)

Control Word 2 (I/O pin functions)

Control Word 3 (flash pulse settings)

Control World 4 (filter settings for overcurrent message)

Control Word 5 (PWM enable and pin selection)

PWM Register

...

...

A/D Interface

Test Register 1

Test Register 2

Test Register 3

Test Control Register

) Reads the inputs or reads back the outputs, depending on I/O pin mode

) For I/O pins in input mode (register is `0' in output mode)

) For I/O pins in output mode (register is `0' in input mode)

) Only writable in input mode

iC-JRX

µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

Rev A1, Page 5/23

Control Word 1 (I/O filters)

Add.: 10

reset entry: 00h

higher nibble

lower nibble

Bit
Name

7
BYPH

6
-

5
FH1

4
FH0

3
BYPL

2
-

1
FL1

0
FL0

higher nibble

Bit 7
BYPH

0
1

I/O filters active

(r)

Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state.

Bit 5..4
FH1..0

FH1

FH0

Filter times

0
0
1
1

0
1
0
1

14.5 × tc(CLK)

± 1 × tc(CLK)

896.5 × tc(CLK)

± 64 × tc(CLK)

3584.5 × tc(CLK)

± 256 × tc(CLK)

7168.5 × tc(CLK)

± 512 × tc(CLK)

lower nibble

Bit 3
BYPL

0
1

I/O filters active

(r)

Bypass for I/O filters: the I/O signals are reprocessed in their unfiltered state.

Bit 1..0
FL1..0

FL1

FL0

Filter times

0
0
1
1

0
1
0
1

14.5 × tc(CLK)

± 1 × tc(CLK)

(r)

896.5 × tc(CLK)

± 64 × tc(CLK)

3584.5 × tc(CLK)

± 256 × tc(CLK)

7168.5 × tc(CLK)

± 512 × tc(CLK)

'-'

Free memory location without a function. Status after a reset is `0'

'xx'h Indicates hexadecimal data for logic states. `x' indicates binary data
(r)

Status after a reset

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