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Электронный компонент: IC41LV16256-60TG

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IC41C16256
IC41LV16256
Integrated Circuit Solution Inc.
1
DR018-0C 04/23/2004
Document Title
256Kx16 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
August 9,2001
0B
Revise for typo on page 20
December 18,2001
0C
Add Pb-free package
April 23,2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 512 cycles /8 ms
Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
Single power supply:
5V 10% (IC41C16256)
3.3V 10% (IC41LV16256)
Byte Write and Byte Read operation via two CAS
Industrail Temperature Range -40
o
C to 85
o
C
Pb-free package is available
DESCRIPTION
The
ICSI
IC41C16256 and IC41LV16256 is a 262,144 x 16-
bit high-performance CMOS Dynamic Random Access Memo-
ries. The IC41C16256 offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as short
as 10 ns per 16-bit word. The Byte Write control, of upper and
lower byte, makes the IC41C16256 ideal for use in
16-, 32-bit wide data bus systems.
These features make the IC41C16256and IC41LV16256 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IC41C16256 is packaged in a 40-pin 400mil SOJ and
400mil TSOP-2.
IC41C16256
IC41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter
-25(5V)
-35
-50
-60
Unit
Max. RAS Access Time (t
RAC
)
25
35
50
60
ns
Max. CAS Access Time (t
CAC
)
8
10
14
15
ns
Max. Column Address Access Time (t
AA
)
12
18
25
30
ns
Min. EDO Page Mode Cycle Time (t
PC
)
10
12
20
25
ns
Min. Read/Write Cycle Time (t
RC
)
45
60
90
110
ns
40-Pin SOJ
PIN CONFIGURATIONS
40-Pin TSOP-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A8
Address Inputs
I/O0-15
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
UCAS
Upper Column Address Strobe
LCAS
Lower Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc.
3
DR018-0C 04/23/2004
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
262,144 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A8
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41C16256
IC41LV16256
4
Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
TRUTH TABLE
Function
RAS
RAS
RAS
RAS
RAS
LCAS
LCAS
LCAS
LCAS
LCAS UCAS
UCAS
UCAS
UCAS
UCAS
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Address t
R
/t
C
I/O
Standby
H
H
H
X
X
X
High-Z
Read: Word
L
L
L
H
L
ROW/COL
D
OUT
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, D
OUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, D
OUT
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
D
IN
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Lower Byte, D
IN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, D
IN
Read-Write
(1,2)
L
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
EDO Page-Mode Read
(2)
1st Cycle:
L
H
L
H
L
H
L
ROW/COL
D
OUT
2nd Cycle:
L
H
L
H
L
H
L
NA/COL
D
OUT
Any Cycle:
L
L
H
L
H
H
L
NA/NA
D
OUT
EDO Page-Mode Write
(1)
1st Cycle:
L
H
L
H
L
L
X
ROW/COL
D
IN
2nd Cycle:
L
H
L
H
L
L
X
NA/COL
D
IN
EDO Page-Mode
1st Cycle:
L
H
L
H
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Read-Write
(1,2)
2nd Cycle:
L
H
L
H
L
H
L
L
H
NA/COL
D
OUT
, D
IN
Hidden Refresh
(2)
Read L
H
L
L
L
H
L
ROW/COL
D
OUT
Write L
H
L
L
L
L
X
ROW/COL
D
OUT
RAS-Only Refresh
L
H
H
X
X
ROW/NA
High-Z
CBR Refresh
(3)
H
L
L
L
X
X
X
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc.
5
DR018-0C 04/23/2004
Functional Description
The IC41C16256 and IC41LV16256 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered 9 bits (A0-A8) at a time. The row address is latched
by the Row Address Strobe (RAS). The column address
is latched by the Column Address Strobe (CAS) .
The IC41C16256 and IC41LV16256 has two CAS controls,
LCAS and UCAS. The LCAS and UCAS inputs internally
generates a CAS signal functioning in an identical man-
ner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IC41C16256 and IC41LV16256 CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IC41C16256 both BYTE READ and
BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the
addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle's falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
V
CC
or be held at a valid V
IH
to avoid current surges.