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IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
1
DR031-0A 10/17/2001
Document Title
64K x16 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
October 17,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC41C1665
IC41LV1665
2
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Fast access and cycle time
TTL compatible inputs and outputs
Refresh Interval: 256 cycles/4 ms
Refresh Mode:
RAS
-Only,
CAS
-before-
RAS
(CBR), Hidden
JEDEC standard pinout
Single power supply:
-- 5V 10% (IC41C1665)
-- 3.3V 10% (IC41LV1665)
Byte Write and Byte Read operation via
two
CAS
Available in 40-pin SOJ and TSOP-2
DESCRIPTION
The
ICSI
IC41C1665 and the IC41LV1665 are 65,536 x 16-
bit high-performance CMOS Dynamic Random Access
Memory. Fast Page Mode allows 256 random accesses
within a single row with access cycle time as short as 12 ns
per 16-bit word. The Byte Write control, of upper and lower
byte, makes these devices ideal for use in 16-, 32-bit wide
data bus systems.
These features make the IC41C1665 and the IC41LV1665
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IC41C1665 and the IC41LV1665 are packaged in a 40-
pin, 400mil SOJ and TSOP-2.
64K x 16 (1-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
NC
A7
A6
A5
A4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
NC
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A7
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
UCAS
Upper Column Address
Strobe
LCAS
Lower Column Address
Strobe
Vcc
Power
GND
Ground
NC
No Connection
40-Pin SOJ
PIN CONFIGURATIONS
40-Pin TSOP-2
KEY TIMING PARAMETERS
Parameter
-25
-30
-35
-40
Unit
Max.
RAS
Access Time (t
RAC
)
25
30
35
40
ns
Max.
CAS
Access Time (t
CAC
)
8
9
10
11
ns
Max. Column Address Access Time (t
AA
) 12
16
18
20
ns
Min. Fast Page Mode Cycle Time (t
PC
)
15
20
23
25
ns
Min. Read/Write Cycle Time (t
RC
)
43
55
65
75
ns
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
3
DR031-0A 10/17/2001
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
65,536 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A7
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41C1665
IC41LV1665
4
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
TRUTH TABLE
Function
R A S
R A S
R A S
R A S
R A S
L C A S
L C A S
L C A S
L C A S
L C A S U C A S
U C A S
U C A S
U C A S
U C A S
W E
W E
W E
W E
W E
O E
O E
O E
O E
O E
Address t
R
/t
C
I/O
Standby
H
H
H
X
X
X
High-Z
Read: Word
L
L
L
H
L
ROW/COL
D
OUT
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte, D
OUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, D
OUT
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
D
IN
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Lower Byte, D
IN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte, D
IN
Read-Write
(1,2)
L
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Hidden Refresh
2)
Read L
H
L
L
L
H
L
ROW/COL
D
OUT
Write L
H
L
L
L
L
X
ROW/COL
D
IN
RAS
-Only Refresh
L
H
H
X
X
ROW/NA
High-Z
CBR Refresh
(3)
H
L
L
L
X
X
X
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either
LCAS
or
UCAS
active).
2. These READ cycles may also be BYTE READ cycles (either
LCAS
or
UCAS
active).
3. At least one of the two CAS signals must be active (
LCAS
or
UCAS
).
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
5
DR031-0A 10/17/2001
FUNCTIONAL DESCRIPTION
The IC41C1665 and the IC41LV1665 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
nine bits (A0-A7) at a time. The row address is latched by the
Row Address Strobe (
RAS
). The column address is latched
by the Column Address Strobe (
CAS
).
RAS
is used to latch
the first eight bits and
CAS
is used to latch the latter eight
bits.
The IC41C1665 and the IC41LV1665 have two
CAS
controls,
LCAS
and
UCAS
. The
LCAS
and
UCAS
inputs internally
generate a
CAS
signal functioning in an identical manner to
the single
CAS
input on the other 64K x 16 DRAMs. The key
difference is that each
CAS
controls its corresponding I/O
tristate logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0 - I/O7 and
UCAS
controls I/O8 - I/O15.
The IC41C1665/IC41LV1665
CAS
function is determined by
the first
CAS
(
LCAS
or
UCAS
) transitioning LOW and the last
transitioning back HIGH. The two
CAS
controls give the
IC41C1665 both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle must
not be initiated until the minimum precharge time t
RP
, t
CP
has
elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are
all satisfied. As a result, the access time is dependent on the
timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs last.
Refresh Cycle
To retain data, 256 refresh cycles are required in each
4 ms period. There are two ways to refresh the memory:
1. By clocking each of the 256 row addresses (A0 through
A7) with
RAS
at least once every 4 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the ad-
dressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
, while
holding
CAS
LOW. In
CAS
-before-
RAS
refresh cycle, an
internal 8-bit counter provides the row addresses and the
external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with V
CC
or be held at a valid V
IH
to avoid current surges.
IC41C1665
IC41LV1665
6
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
V
V
CC
Supply Voltage
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
V
I
OUT
Output Current
50
mA
P
D
Power DICSIpation
1
W
T
A
Operation Temperature
Com.
0 to +70
o
C
Ind.
-40 to +85
o
C
T
STG
Storage Temperature
55 to +125
o
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
5V
4.5
5.0
5.5
V
3.3V
3.0
3.3
3.6
V
V
IH
Input High Voltage
5V
2.4
--
V
CC
+ 1.0
V
3.3V
2.0
--
V
CC
+ 0.3
V
V
IL
Input Low Voltage
5V
1.0
--
0.8
V
3.3V
0.3
--
0.8
V
T
A
Ambient Temperature
Com.
0
--
70
o
C
Ind.
40
--
85
o
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A7
5
pF
C
IN
2
Input Capacitance:
RAS
,
UCAS
,
LCAS
,
WE
,
OE
7
pF
C
IO
Data Input/Output Capacitance: I/O0-I/O15
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
o
C, f = 1 MHz, V
CC
= 5.0V + 10%, or V
CC
= 3.3V + 10%.
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
7
DR031-0A 10/17/2001
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
V
IN
Vcc
10
10
A
Other inputs not under test = 0V
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
10
10
A
0V
V
OUT
Vcc
V
OH
Output High Voltage Level
I
OH
= 5 mA
2.4
--
V
V
OL
Output Low Voltage Level
I
OL
= +4.2 mA
--
0.4
V
I
CC
1
Stand-by Current: TTL
RAS
,
LCAS
,
UCAS
V
IH
5V
--
2
mA
mA
I
CC
1
Stand-by Current: TTL
RAS
,
LCAS
,
UCAS
V
IH
3.3V
--
1
mA
mA
I
CC
2
Stand-by Current: CMOS
RAS
,
LCAS
,
UCAS
V
CC
0.2V
5V
--
1
mA
I
CC
2
Stand-by Current: CMOS
RAS
,
LCAS
,
UCAS
V
CC
0.2V
3.3V
--
0.5
mA
I
CC
3
Operating Current:
RAS
,
LCAS
,
UCAS
,
-25
--
170
mA
Random Read/Write
(2,3,4)
Address Cycling, t
RC
= t
RC
(min.)
-30
--
150
Average Power Supply Current
-35
--
130
-40
--
120
I
CC
4
Operating Current:
RAS
= V
IL
,
LCAS
,
UCAS
,
-25
--
170
mA
Fast Page Mode
(2,3,4)
Cycling t
PC
= t
PC
(min.)
-30
--
150
Average Power Supply Current
-35
--
130
-40
--
120
I
CC
5
Refresh Current:
RAS
Cycling,
LCAS
,
UCAS
V
IH
-25
--
170
mA
RAS
-Only
(2,3)
t
RC
= t
RC
(min.)
-30
--
150
Average Power Supply Current
-35
--
130
-40
--
120
I
CC
6
Refresh Current:
RAS
,
LCAS
,
UCAS
Cycling
-25
--
170
mA
CBR
(2,3,5)
t
RC
= t
RC
(min.)
-30
--
150
Average Power Supply Current
-35
--
130
-40
--
120
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper
device operation is assured.The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is
exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
IC41C1665
IC41LV1665
8
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25
-30
-35
-40
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Units
t
RC
Random READ or WRITE Cycle Time
43
--
55
--
65
--
75
--
ns
t
RAC
Access Time from
RAS
(6, 7)
--
25
--
30
--
35
--
40
ns
t
CAC
Access Time from
CAS
(6, 8, 15)
--
8
--
9
--
10
--
11
ns
t
AA
Access Time from Column-Address
(6)
--
12
--
16
--
18
--
20
ns
t
RAS
RAS
Pulse Width
25
10k
30
10K
35
10K
40
10K
ns
t
RP
RAS
Precharge Time
15
--
20
--
23
--
25
--
ns
t
CAS
CAS
Pulse Width
(26)
4
10k
9
10K
10
10K
11
10K
ns
t
CP
CAS
Precharge Time
(9, 25)
4
--
5
--
6
--
7
--
ns
t
CSH
CAS
Hold Time
(21)
21
--
30
--
35
--
40
--
ns
t
RCD
RAS
to
CAS
Delay Time
(10, 20)
10
17
10
21
10
25
10
29
ns
t
ASR
Row-Address Setup Time
0
--
0
--
0
--
0
--
ns
t
RAH
Row-Address Hold Time
5
--
5
--
5
--
5
--
ns
t
ASC
Column-Address Setup Time
(20)
0
--
0
--
0
--
0
--
ns
t
CAH
Column-Address Hold Time
(20)
5
--
5
--
5
--
5
--
ns
t
AR
Column-Address Hold Time
22
--
26
--
30
--
34
--
ns
(referenced to
RAS
)
t
RAD
RAS
to Column-Address Delay Time
(11)
8
13
8
14
8
17
8
20
ns
t
RAL
Column-Address to
RAS
Lead Time
12
--
16
--
18
--
20
--
ns
t
RPC
RAS
to
CAS
Precharge Time
10
--
10
--
10
--
10
--
ns
t
RSH
RAS
Hold Time
(27)
8
--
9
--
10
--
11
--
ns
t
CLZ
CAS
to Output in Low-Z
(15, 29)
3
--
3
--
3
--
3
--
ns
t
CRP
CAS
to
RAS
Precharge Time
(21)
5
--
5
--
5
--
5
--
ns
t
OD
Output Disable Time
(19, 28, 29)
--
6
--
8
--
8
--
8
ns
t
OE
Output Enable Time
(15, 16)
--
8
--
9
--
10
--
11
ns
t
OES
OE
LOW to
CAS
HIGH Setup Time
5
--
5
--
5
--
5
--
ns
t
RCS
Read Command Setup Time
(17, 20)
0
--
0
--
0
--
0
--
ns
t
RRH
Read Command Hold Time
0
--
0
--
0
--
0
--
ns
(referenced to
RAS
)
(12)
t
RCH
Read Command Hold Time
0
--
0
--
0
--
0
--
ns
(referenced to
CAS
)
(12, 17, 21)
t
WCH
Write Command Hold Time
(17, 27)
5
--
5
--
5
--
5
--
ns
t
WCR
Write Command Hold Time
22
--
26
--
30
--
34
--
ns
(referenced to
RAS
)
(17)
t
WP
Write Command Pulse Width
(17)
5
--
5
--
5
--
5
--
ns
t
RWL
Write Command to
RAS
Lead Time
(17)
7
--
8
--
9
--
10
--
ns
t
CWL
Write Command to
CAS
Lead Time
(17, 21)
5
--
6
--
7
--
8
--
ns
t
WCS
Write Command Setup Time
(14, 17, 20)
0
--
0
--
0
--
0
--
ns
t
DHR
Data-in Hold Time (referenced to
RAS
)
22
--
26
--
30
--
34
--
ns
(Continued)
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
9
DR031-0A 10/17/2001
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25
-30
-35
-40
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Units
t
ACH
Column-Address Setup Time to
CAS
15
--
15
--
15
--
15
--
ns
Precharge during WRITE Cycle
t
OEH
OE
Hold Time from
WE
during
4
--
4
--
4
--
5
--
ns
READ-MODIFY-WRITE cycle
(18)
t
DS
Data-In Setup Time
(15, 22)
0
--
0
--
0
--
0
--
ns
t
DH
Data-In Hold Time
(15, 22)
5
--
5
--
5
--
5
--
ns
t
RWC
READ-MODIFY-WRITE Cycle Time
65
--
85
--
95
--
105
--
ns
t
RWD
RAS
to
WE
Delay Time during
34
--
46
--
51
--
56
--
ns
READ-MODIFY-WRITE Cycle
(14)
t
CWD
CAS
to
WE
Delay Time
(14, 20)
17
--
25
--
26
--
27
--
ns
t
AWD
Column-Address to
WE
Delay Time
(14)
21
--
32
--
34
--
36
--
ns
t
PC
Fast Page Mode READ or WRITE
15
--
20
--
23
--
25
--
ns
Cycle Time
(24)
t
RASP
Fast Page Mode
RAS
Pulse Width
25
10k
30
10K
35
10K
40
10K
ns
t
CPA
Access Time from
CAS
Precharge
(15)
--
14
--
18
--
20
--
22
ns
t
PRWC
Fast Page Mode READ-WRITE Cycle Time
(24)
37
--
42
--
49
--
52
--
ns
t
OFF
Output Buffer Turn-Off Delay from
3
15
3
15
3
15
3
15
ns
CAS
or
RAS
(13,15,19, 29)
t
CLCH
Last
CAS
going LOW to First
CAS
4
--
9
--
10
--
11
--
ns
returning HIGH
(23)
t
CSR
CAS
Setup Time (CBR REFRESH)
(30, 20)
5
--
10
--
10
--
10
--
ns
t
CHR
CAS
Hold Time (CBR REFRESH)
(30, 21)
7
--
10
--
10
--
10
--
ns
t
ORD
OE
Setup Time prior to
RAS
during
0
--
0
--
0
--
0
--
ns
HIDDEN REFRESH Cycle
t
REF
Refresh Period (256 Cycles)
--
4
--
4
--
4
--
4
ms
t
T
Transition Time (Rise or Fall)
(2, 3)
1
50
1
50
1
50
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V 10%)
One TTL Load and 50 pF (Vcc = 3.3V 10%)
Input timing reference levels: V
IH
= 2.4V, V
IL
= 0.8V (Vcc = 5.0V 10%);
V
IH
= 2.0V, V
IL
= 0.8V (Vcc = 3.3V 10%)
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V (Vcc = 5V 10%, 3.3V 10%)
IC41C1665
IC41LV1665
10
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycle (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
IH
and V
IL
(or between V
IL
and V
IH
) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
4. If
CAS
and
RAS
= V
IH
, data output is High-Z.
5. If
CAS
= V
IL
, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
RCD
t
RCD
(MAX). If t
RCD
is greater than the maximum recommended value shown in this table, t
RAC
will increase
by the amount that t
RCD
exceeds the value shown.
8. Assumes that t
RCD
t
RCD
(MAX).
9. If
CAS
is LOW at the falling edge of
RAS
, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer,
CAS
and
RAS
must be pulsed for t
CP
.
10. Operation with the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference point only; if t
RCD
is greater than the specified t
RCD
(MAX) limit, access time is controlled exclusively by t
CAC
.
11. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference point only; if t
RAD
is greater than the specified t
RAD
(MAX) limit, access time is controlled exclusively by t
AA
.
12. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
13. t
OFF
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
.
14. t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
WCS
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
RWD
t
RWD
(MIN), t
AWD
t
AWD
(MIN) and t
CWD
t
CWD
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
CAS
and
RAS
or
OE
go back
to V
IH
) is indeterminate.
OE
held HIGH and
WE
taken LOW after
CAS
goes LOW result in a LATE WRITE (
OE
-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding
CAS
input, I/O0-I/O7 by
LCAS
and I/O8-I/O15 by
UCAS
.
16. During a READ cycle, if
OE
is LOW then taken HIGH before
CAS
goes HIGH, I/O goes open. If
OE
is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as
WE
going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD
and t
OEH
met (
OE
HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if
CAS
remains LOW
and
OE
is taken back to LOW after t
OEH
is met.
19. The I/Os are in open during READ cycles once t
OD
or t
OFF
occur.
20. The first
CAS
edge to transition LOW.
21. The last
CAS
edge to transition HIGH.
22. These parameters are referenced to
CAS
leading edge in EARLY WRITE cycles and
WE
leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling
CAS
edge to first rising
CAS
edge.
24. Last rising
CAS
edge to next cycles last rising
CAS
edge.
25. Last rising
CAS
edge to first falling
CAS
edge.
26. Each
CAS
must meet minimum pulse width.
27. Last
CAS
to go LOW.
28. I/Os controlled, regardless
UCAS
and
LCAS
.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
11
DR031-0A 10/17/2001
READ CYCLE
Note:
1. t
OFF
is referenced from rising edge of
RAS
or
CAS
, whichever occurs last.
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
UCAS-LCAS
RAS
Row
Column
Row
Open
Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF
(1)
t
RAC
t
CLZ
t
OES
t
OE
t
OD
Don't Care
IC41C1665
IC41LV1665
12
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O
Open
Open
Valid D
OUT
Valid D
IN
Don't Care
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
13
DR031-0A 10/17/2001
EARLY WRITE CYCLE
(
OE
= DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don't Care
IC41C1665
IC41LV1665
14
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
FAST PAGE MODE READ CYCLE
Don't Care
OUT
t
AR
I/O
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Column
Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PC
t
RCD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
CAC
t
AA
t
CLZ
t
RAC
t
OE
t
CLZ
t
CAC
t
OE
t
CAC
t
OE
OUT
OUT
t
OD
t
OD
t
OD
t
CLZ
t
AA
t
CPA
t
AA
t
CPA
t
RAH
t
CAH
t
CRP
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
15
DR031-0A 10/17/2001
FAST PAGE MODE READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE Cycles)
Don't Care
OUT
t
AR
t
RWD
t
AWD
I/O0-I/O15
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Column
Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PRWC
t
RCD
t
CWD
t
CWD
t
CWD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
AWD
t
AWD
t
CAC
t
AA
t
DH
t
CLZ
t
RAC
t
DH
t
DH
t
OE
t
CLZ
t
CAC
t
OE
t
CAC
t
OE
OUT
OUT
IN
IN
IN
t
OEZ
t
OEZ
t
OED
t
OED
t
DS
t
OEZ
t
OED
t
DS
t
CLZ
t
AA
t
AA
t
WP
t
RAH
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RWL
t
CPWD
t
CPWD
t
CAH
t
CRP
t
DS
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Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
FAST PAGE MODE EARLY WRITE CYCLE
Don't Care
t
AR
I/O0-I/O15
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row
Column
Column
Column
t
AR
t
CWL
t
WCR
t
DHR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
RHCP
t
PC
t
RCD
t
CRP
t
ASR
t
WCS
t
DS
t
RAD
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
WCH
t
DH
t
DS
t
DS
t
DH
t
DH
t
CP
t
CP
t
RP
t
CAH
t
RAH
t
CAH
t
CRP
t
CWL
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
CWL
t
WCH
t
WP
Valid D
IN
Valid D
IN
Valid D
IN
AC WAVEFORMS
RAS
RAS
RAS
RAS
RAS-ONLY REFRESH CYCLE
(
OE
,
WE
= DON'T CARE)
t
RAS
t
RC
t
RP
I/O
ADDRESS
UCAS/LCAS
RAS
Row
Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don't Care
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
17
DR031-0A 10/17/2001
CBR REFRESH CYCLE
(Addresses;
WE
,
OE
= DON'T CARE)
t
RAS
t
RAS
t
RP
t
RP
I/O
UCAS/LCAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
HIDDEN REFRESH CYCLE
(1)
(
WE
= HIGH;
OE
= LOW)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case,
WE
= LOW and
OE
= HIGH.
2. t
OFF
is referenced from rising edge of
RAS
or
CAS
, whichever occurs last.
t
RAS
t
RAS
t
RP
UCAS/LCAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS
Row
Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O
Open
Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don't Care
IC41C1665
IC41LV1665
18
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
ORDERING INFORMATION
IC41LV1665
Commercial Range: 0


C to 70C
Speed (ns) Order Part No.
Package
25
IC41LV1665-25K
400mil SOJ
IC41LV1665-25T
400mil T SOP-2
30
IC41LV1665-30K
400mil SOJ
IC41LV1665-30T
400mil T SOP-2
35
IC41LV1665-35K
400mil SOJ
IC41LV1665-35T
400mil T SOP-2
40
IS41LV1665-40K
400mil SOJ
IC41LV1665-40T
400mil T SOP-2
Industrial Range: -40


C to 85C
Speed (ns) Order Part No.
Package
25
IC41LV1665-25KI
400mil SOJ
IC41LV1665-25TI
400mil TSOP-2
30
IC41LV1665-30KI
400mil SOJ
IC41LV1665-30TI
400mil TSOP-2
35
IC41LV1665-35KI
400mil SOJ
IC41LV1665-35TI
400mil TSOP-2
40
IC41LV1665-40KI
400mil SOJ
IC41LV1665-40TI
400mil TSOP-2
ORDERING INFORMATION
IC41C1665
Commercial Range: 0


C to 70C
Speed (ns) Order Part No.
Package
25
IC41C1665-25K
400mil SOJ
IC41C1665-25T
400mil TSOP-2
30
IC41C1665-30K
400mil SOJ
IC41C1665-30T
400mil TSOP-2
35
IC41C1665-35K
400mil SOJ
IC41C1665-35T
400mil TSOP-2
40
IC41C1665-40K
400mil SOJ
IC41C1665-40T
400mil TSOP-2
Industrial Range: -40


C to 85C
Speed (ns) Order Part No.
Package
25
IC41C1665-25KI
400mil SOJ
IC41C1665-25TI
400mil TSOP-2
30
IC41C1665-30KI
400mil SOJ
IC41C1665-30TI
400mil TSOP-2
35
IC41C1665-35KI
400mil SOJ
IC41C1665-35TI
400mil TSOP-2
40
IC41C1665-40KI
400mil SOJ
IC41C1665-40TI
400mil TSOP-2
IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
19
DR031-0A 10/17/2001
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
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