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Электронный компонент: IC41LV82052S-60J

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.EATURES
.AST Page Mode access cycle
TTL compatible inputs and outputs
Refresh Interval:
Refresh Mode: 4)5-Only,
+)5-before-4)5 (CBR), and Hidden,
2,048 cycles/32 ms
Self refresh Mode 2,048 cycles/128 ms
JEDEC standard pinout
Single power supply:
5V10% or 3.3V 10%
Byte Write and Byte Read operation via
+)5
DESCRIPTION
The
1+51
82052S Series is a 2,097,152 x 8-bit high-perfor-
mance CMOS Dynamic Random Access Memory. The .ast
Page Mode allows 2,048 random accesses within a single row
with access cycle time as short as 20 ns per 8-bit word.
These features make the 82052S Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 82052S Series is packaged in a 28-pin 300mil SOJ and a
28 pin TSOP-2
IC41C82052S
IC41LV82052S
2M x 8 (16-MBIT) DYNAMIC
RAM
WITH .AST PAGE MODE
Integrated Circuit Solution Inc.
1
DR016-0A 06/12/2001
KEY TIMING PARAMETERS
Parameter
-50
-60 Unit
RAS Access Time (t
RAC
)
50
60
ns
CAS Access Time (t
CAC
)
13
15
ns
Column Address Access Time (t
AA
)
25
30
ns
EDO Page Mode Cycle Time (t
PC
)
20
25
ns
Read/Write Cycle Time (t
RC
)
84
104
ns
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IC41C82052S
2K
5V 10%
IC41LV82052S
2K
3.3V 10%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
Address Inputs
I/O0-7
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
PIN CON.IGURATION
28 Pin SOJ, TSOP-2
IC41C82052S
IC41LV82052S
2
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
.UNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
2,097,152 x 8
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O7
RAS
RAS
A0-A10
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
.unction
RAS
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CAS
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Address t
R
/t
C
I/O
Standby
H
H
X
X
X
High-Z
Read
L
L
H
L
ROW/COL
D
OUT
Write: Word (Early Write)
L
L
L
X
ROW/COL
D
IN
Read-Write
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Hidden Refresh
Read
L
H
L
L
H
L
ROW/COL
D
OUT
Write
(1)
L
H
L
L
L
X
ROW/COL
D
OUT
RAS-Only Refresh
L
H
X
X
ROW/NA
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
Note:
1. EARLY WRITE only.
IC41C82052S
IC41LV82052S
Integrated Circuit Solution Inc.
3
DR016-0A 06/12/2001
.unctional Description
The IC41C82052S and IC41LV82052S are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These
are entered 11 bits (A0-A10) at a time for the 2K refresh
device. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 62.5 s per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified t
RAS
.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of t
RP
. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 2,048 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
V
CC
or be held at a valid V
IH
to avoid current surges.
IC41C82052S
IC41LV82052S
4
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
V
CC
Supply Voltage
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
I
OUT
Output Current
50
mA
P
D
Power Dissipation
1
W
T
A
Commercial Operation Temperature
0 to +70
C
T
STG
Storage Temperature
55 to +125
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
5V
4.5
5.0
5.5
V
3.3V
3.0
3.3
3.6
V
IH
Input High Voltage
5V
2.4
V
CC
+ 1.0
V
3.3V
2.0
V
CC
+ 0.3
V
IL
Input Low Voltage
5V
1.0
0.8
V
3.3V
0.3
0.8
T
A
Commercial Ambient Temperature
0
70
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A10
5
p.
C
IN
2
Input Capacitance: RAS, CAS, WE, OE
7
p.
C
IO
Data Input/Output Capacitance: I/O0-I/O7
7
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz.
IC41C82052S
IC41LV82052S
Integrated Circuit Solution Inc.
5
DR016-0A 06/12/2001
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V < V
IN
< Vcc
5
5
A
Other inputs not under test = 0V
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
5
5
A
0V < V
OUT
< Vcc
V
OH
Output High Voltage Level
I
OH
= 5.0 mA with V
CC
=5V
2.4
V
I
OH
= 2.0 mA with V
CC
=3.3V
V
OL
Output Low Voltage Level
I
OL
= 4.2 mA with V
CC
=5V
0.4
V
I
OL
= 2 mA with V
CC
=3.3V
I
CC
1
Standby Current: TTL
RAS, CAS > V
IH
5V
2
mA
3.3V
0.5
I
CC
2
Standby Current: CMOS
RAS, CAS > V
CC
0.2V
5V
1
mA
3.3V
0.5
I
CC
3
Operating Current:
RAS, CAS,
-50
120
mA
Random Read/Write
(2,3,4)
Address Cycling, t
RC
= t
RC
(min.)
-60
110
Average Power Supply Current
I
CC
4
Operating Current:
RAS = V
IL
, CAS,
-50
90
mA
.ast Page Mode
(2,3,4)
t
RC
= t
RC
(min.)
-60
80
Average Power Supply Current
I
CC
5
Refresh Current:
RAS Cycling, CAS > V
IH
-50
120
mA
RAS-Only
(2,3)
t
RC
= t
RC
(min.)
-60
110
Average Power Supply Current
I
CC
6
Refresh Current:
RAS, CAS Cycling
-50
120
mA
CBR
(2,3,5)
t
RC
= t
RC
(min.)
-60
110
Average Power Supply Current
Iccs
Self Refrsh Current
Self Refresh Mode
5V
400
A
3.3V
300
A
Notes:
1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
RE.
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.