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IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
1
DR035-0B 7/31/2002
Document Title
4Mx4 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
June 14,2002
Preliminary
0B
Chang working range from V
CC
=1.9V~2.4V
July 31,2002
to V
CC
=1.9V~2.7V, V
IH
=1.4V to V
IH
=1.6V
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC41SV44052
IC41SV44054
2
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
FEATURES
Fast Page Mode Access Cycle
TTL compatible inputs and outputs
Refresh Interval:
-- 2,048 cycles/32 ms
-- 4,096 cycles/64 ms
Refresh Mode:
RAS
-Only,
CAS
-before-
RAS
(CBR), and Hidden
JEDEC standard pinout
Single power supply:
1.9V
-
-
-
-
-
2.7V
DESCRIPTION
The
ICSI
44052/44054 Series is a 4,194,304 x 4-bit high-
performance CMOS Dynamic Random Access Memory. The
Fast Page Mode allows 2,048 or 4,096 random accesses within
a single row with access cycle time as short as 20 ns per 4-bit
word.
These features make the 44052/44054 Series ideally suited for
digital signal processing, and low power portable audio
applications.
The 44052/44054 Series is packaged in a 26-pin 300mil SOJ
and a 26 pin TSOP-2
4M x 4 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
KEY TIMING PARAMETERS
Parameter
-70
-
100 Unit
RAS
Access Time (t
RAC
)
70
100
ns
CAS
Access Time (t
CAC
)
20
25
ns
Column Address Access Time (t
AA
)
35
50
ns
Fast Page Mode Cycle Time (t
PC
)
45
60
ns
Read/Write Cycle Time (t
RC
)
130 180
ns
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
PIN DESCRIPTIONS
A0-A11
Address Inputs (4K Refresh)
A0-A10
Address Inputs (2K Refresh)
I/O0-3
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Vcc
Power
GND
Ground
PIN CONFIGURATION
24 (26) Pin SOJ, TSOP
-
2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O0
I/O1
WE
RAS
*A11(NC)
A10
A0
A1
A2
A3
VCC
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
Preliminary
*A11 is NC for 2K Refresh devices.
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
3
DR035-0B 7/31/2002
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
Function
RAS
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CAS
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Address t
R
/t
C
I/O
Standby
H
H
X
X
X
High-Z
Read
L
L
H
L
ROW/COL
D
OUT
Write: Word (Early Write)
L
L
L
X
ROW/COL
D
IN
Read-Write
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Hidden Refresh
Read
L
H
L
L
H
L
ROW/COL
D
OUT
Write
(1)
L
H
L
L
L
X
ROW/COL
D
IN
RAS
-Only Refresh
L
H
X
X
ROW/NA
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
Note:
1.
EARLY WRITE only.
OE
WE
CAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
4,194,304 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A10
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41SV44052
IC41SV44054
4
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
Functional Description
The IC41SV44052 and IC41LV44054 are CMOS DRAMs
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 or 12 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
or 12 bits (A0-A11) at a time for the 4K refresh device. The
row address is latched by the Row Address Strobe (
RAS
).
The column address is latched by the Column Address
Strobe (
CAS
).
RAS
is used to latch the first nine bits and
CAS
is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle
must not be initiated until the minimum precharge time t
RP
,
t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The col-
umn address must be held for a minimum time specified by
t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and
t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through A11)
with RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 11(12)-bit counter provides the row
addresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power
-
On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initializa-
tion cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
5
DR035-0B 7/31/2002
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND
-
0.5 to +3.0
V
V
CC
Supply Voltage
-
0.5 to +3.0
V
I
OUT
Output Current
50
mA
P
D
Power Dissipation
0.2
W
T
A
Commercial Operation Temperature
-10 to +70
o
C
T
STG
Storage Temperature
-
55 to +125
o
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Max.
Unit
V
CC
Supply Voltage 1.9 2.7 V
V
IH
Input High Voltage
1.6
V
CC
+ 0.3
V
V
IL
Input Low Voltage
-
0.3
0.6
V
T
A
Commercial Ambient Temperature
-10
70
o
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A10
5
pF
C
IN
2
Input Capacitance:
RAS
,
CAS
,
WE
,
OE
7
pF
C
IO
Data Input/Output Capacitance: I/O0-I/O3
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
o
C, f = 1 MHz.
IC41SV44052
IC41SV44054
6
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
V
IN
Vcc
-
5
5
A
Other inputs not under test = 0V
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
-
5
5
A
0V
V
OUT
Vcc
V
OH
Output High Voltage Level
I
OH
=
-
2.0 mA
1.6
-
V
V
OL
Output Low Voltage Level
I
OL
= 2 mA
-
0.8
V
I
CC
1
Standby Current: TTL
RAS
,
CAS
V
IH
-
1
mA
I
CC
2
Standby Current: CMOS
RAS
,
CAS
V
CC
-
0.2V
0.5
mA
I
CC
3
Operating Current:
RAS
,
CAS
,
-70
-
60
mA
Random Read/Write
(2,3,4)
Address Cycling, t
RC
= t
RC
(min.)
-100
-
50
Average Power Supply Current
I
CC
4
Operating Current:
RAS
= V
IL
,
CAS
V
IH
-70
-
45
mA
Fast Page Mode
(2,3,4)
t
RC
= t
RC
(min.)
-100
-
35
Average Power Supply Current
I
CC
5
Refresh Current:
RAS
Cycling,
CAS
V
IH
-70
-
60
mA
RAS
-Only
(2,3)
t
RC
= t
RC
(min.)
-100
-
50
Average Power Supply Current
I
CC
6
Refresh Current:
RAS
,
CAS
Cycling
-70
-
60
mA
CBR
(2,3,5)
t
RC
= t
RC
(min.)
-100
-
50
Average Power Supply Current
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
7
DR035-0B 7/31/2002
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-
70
-
100
Symbol
Parameter
Min.
Max.
Min.
Max. Units
t
RC
Random READ or WRITE Cycle Time
130
-
180
-
ns
t
RAC
Access Time from
RAS
(6, 7)
-
70
-
100
ns
t
CAC
Access Time from
CAS
(6, 8, 15)
-
20
-
25
ns
t
AA
Access Time from Column-Address
(6)
-
35
-
50
ns
t
RAS
RAS
Pulse Width
70
10K
100
10K
ns
t
RP
RAS
Precharge Time
50
-
70
-
ns
t
CAS
CAS
Pulse Width
(23)
20
10K
25
10K
ns
t
CP
CAS
Precharge Time
(9)
10
-
10
-
ns
t
CSH
CAS
Hold Time
(21)
70
-
100
-
ns
t
RCD
RAS
to
CAS
Delay Time
(10, 20)
20
50
25
75
ns
t
ASR
Row-Address Setup Time
0
-
0
-
ns
t
RAH
Row-Address Hold Time
10
-
15
-
ns
t
ASC
Column-Address Setup Time
(20)
0
-
0
-
ns
t
CAH
Column-Address Hold Time
(20)
15
-
20
-
ns
t
AR
Column-Address Hold Time
70
-
100
-
ns
(referenced to
RAS
)
t
RAD
RAS
to Column-Address Delay Time
(11)
15
35
20
50
ns
t
RAL
Column-Address to
RAS
Lead Time
35
-
50
-
ns
t
RPC
RAS
to
CAS
Precharge Time
5
-
5
-
ns
t
RSH
RAS
Hold Time
20
-
25
-
ns
t
CLZ
CAS
to Output in Low-Z
(15, 24)
3
-
3
-
ns
t
CRP
CAS
to
RAS
Precharge Time
(21)
5
-
5
-
ns
t
OD
Output Disable Time
(19, 24)
3
20
3
25
ns
t
OE
Output Enable Time
(15, 16)
-
20
-
25
ns
t
OES
OE
LOW to
CAS
HIGH Setup Time
5
-
5
-
ns
t
RCS
Read Command Setup Time
(17, 20)
0
-
0
-
ns
t
RRH
Read Command Hold Time
0
-
0
-
ns
(referenced to
RAS
)
(12)
t
RCH
Read Command Hold Time
0
-
0
-
ns
(referenced to
CAS
)
(12, 17, 21)
t
WCH
Write Command Hold Time
(17)
10
-
15
-
ns
t
WCR
Write Command Hold Time
70
-
100
-
ns
(referenced to
RAS
)
(17)
t
WP
Write Command Pulse Width
(17)
10
-
15
-
ns
t
RWL
Write Command to
RAS
Lead Time
(17)
20
-
25
-
ns
t
CWL
Write Command to
CAS
Lead Time
(17, 21)
20
-
25
-
ns
t
WCS
Write Command Setup Time
(14, 17, 20)
0
-
0
-
ns
t
DHR
Data-in Hold Time (referenced to
RAS
)
50
-
60
-
ns
IC41SV44052
IC41SV44054
8
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
AC CHARACTERISTICS
(Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-
70
-
100
Symbol
Parameter
Min. Max. Min.
Max.
Units
t
ACH
Column-Address Setup Time to
CAS
15
-
15
-
ns
Precharge during WRITE Cycle
t
OEH
OE
Hold Time from
WE
during
20
-
25
-
ns
READ-MODIFY-WRITE cycle
(18)
t
DS
Data-In Setup Time
(15, 22)
0
-
0
-
ns
t
DH
Data-In Hold Time
(15, 22)
15
-
20
-
ns
t
RWC
READ-MODIFY-WRITE Cycle Time
185
-
240
-
ns
t
RWD
RAS
to
WE
Delay Time during
100
-
130
-
ns
READ-MODIFY-WRITE Cycle
(14)
t
CWD
CAS
to
WE
Delay Time
(14, 20)
45
-
55
-
ns
t
AWD
Column-Address to
WE
Delay Time
(14)
60
-
85
-
ns
t
PC
Fast Page Mode READ or WRITE
45
-
60
-
ns
Cycle Time
t
RASP
Fast Page Mode
RAS
Pulse Width
70
100K
100
100K
ns
t
CPA
Access Time from
CAS
Precharge
(15)
-
40
-
55
ns
t
PRWC
Fast Page Mode READ WRITE
100
-
120
-
ns
Cycle Time
t
OFF
Output Buffer Turn-Off Delay from
3
15
3
15
ns
CAS
or
RAS
(13,15,19, 24)
t
CSR
CAS
Setup Time (CBR REFRESH)
(20, 25)
5
-
5
-
ns
t
CHR
CAS
Hold Time (CBR REFRESH)
( 21, 25)
10
-
10
-
ns
t
ORD
OE
Setup Time prior to
RAS
during
0
-
0
-
ns
HIDDEN REFRESH Cycle
t
REF
Auto Refresh Period 2,048 Cycles
-
32
-
32 ms
Auto Refresh Period 4,096 Cycles
-
64
-
64
ms
t
T
Transition Time (Rise or Fall)
(2, 3)
3
50
3
50
ns
AC TEST CONDITIONS
Output load:
One TTL Load and 100 pF
Input timing reference levels:
V
IH
= 1.6V, V
IL
= 0.6V
Output timing reference levels: V
OH
= 1.6V, V
OL
= 0.8V
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
9
DR035-0B 7/31/2002
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycle (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
IH
and V
IL
(or between V
IL
and V
IH
) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
4. If
CAS
and
RAS
= V
IH
, data output is High-Z.
5. If
CAS
= V
IL
, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
RCD
t
RCD
(MAX). If t
RCD
is greater than the maximum recommended value shown in this table, t
RAC
will increase
by the amount that t
RCD
exceeds the value shown.
8. Assumes that t
RCD
t
RCD
(MAX).
9. If
CAS
is LOW at the falling edge of
RAS
, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer,
CAS
and
RAS
must be pulsed for t
CP
.
10. Operation with the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference point only; if t
RCD
is greater than the specified t
RCD
(MAX) limit, access time is controlled exclusively by t
CAC
.
11. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference point only; if t
RAD
is greater than the specified t
RAD
(MAX) limit, access time is controlled exclusively by t
AA
.
12. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
13. t
OFF
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
.
14. t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
WCS
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
RWD
t
RWD
(MIN), t
AWD
t
AWD
(MIN) and t
CWD
t
CWD
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
CAS
and
RAS
or
OE
go back
to V
IH
) is indeterminate.
OE
held HIGH and
WE
taken LOW after
CAS
goes LOW result in a LATE WRITE (
OE
-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding
CAS
input.
16. During a READ cycle, if
OE
is LOW then taken HIGH before
CAS
goes HIGH, I/O goes open. If
OE
is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as
WE
going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD
and t
OEH
met (
OE
HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if
CAS
remains LOW
and
OE
is taken back to LOW after t
OEH
is met.
19. The I/Os are in open during READ cycles once t
OD
or t
OFF
occur.
20. Determined by falling edge of
CAS
.
21. Determined by rising edge of
CAS
.
22. These parameters are referenced to
CAS
leading edge in EARLY WRITE cycles and
WE
leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23.
CAS
must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
IC41SV44052
IC41SV44054
10
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
Don't Care
READ CYCLE
Note:
1. t
OFF
is referenced from rising edge of
RAS or CAS, whichever occurs last.
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Row
Open
Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF
(1)
t
RAC
t
CLZ
t
OES
t
OE
t
OD
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
11
DR035-0B 7/31/2002
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE Cycles)
Don't Care
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O
Open
Open
Valid D
OUT
Valid D
IN
IC41SV44052
IC41SV44054
12
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
EARLY WRITE CYCLE
(
OE
= DON'T CARE)
Don't Care
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
13
DR035-0B 7/31/2002
FAST PAGE MODE READ CYCLE
Don't Care
OUT
t
AR
I/O
WE
OE
ADDRESS
CAS
RAS
Row
Column
Column
Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PC
t
RCD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
CAC
t
AA
t
CLZ
t
RAC
t
OE
t
CLZ
t
CAC
t
OE
t
CAC
t
OE
OUT
OUT
t
OD
t
OD
t
OD
t
CLZ
t
AA
t
AA
t
RAH
t
CAH
t
CRP
t
CPA
t
CPA
IC41SV44052
IC41SV44054
14
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
FAST PAGE MODE EARLY WRITE CYCLE
Don't Care
t
AR
I/O
WE
OE
ADDRESS
CAS
RAS
Row
Column
Column
Column
t
AR
t
CWL
t
WCR
t
DHR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PC
t
RCD
t
CRP
t
ASR
t
WCS
t
DS
t
RAD
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
WCH
t
DH
t
DS
t
DS
t
DH
t
DH
t
CP
t
CP
t
RP
t
CAH
t
RAH
t
CAH
t
CRP
t
CWL
t
WCS
t
WCS
t
WCH
t
WP
t
WP
t
RWL
t
WCH
t
WP
Valid D
IN
Valid D
IN
Valid D
IN
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
15
DR035-0B 7/31/2002
RAS
RAS
RAS
RAS
RAS
-
ONLY REFRESH CYCLE
(
OE
,
WE
= DON'T CARE)
t
RAS
t
RC
t
RP
I/O
ADDRESS
CAS
RAS
Row
Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don't Care
FAST PAGE MODE READ WRITE CYCLE (
LATE WRITE AND READ-MODIFY-WRITE CYCLE
)
Don't Care
OUT
t
AR
t
RWD
t
AWD
I/O
WE
OE
ADDRESS
CAS
RAS
Row
Column
Column
Column
t
AR
t
CSH
t
CAS
t
CAS
t
CAS
t
RASP
t
RSH
t
PRWC
t
RCD
t
CWD
t
CWD
t
CWD
t
CRP
t
ASR
t
RAD
t
RCS
t
ASC
t
ASC
t
ASC
t
RAL
t
CAH
t
CP
t
CP
t
RP
t
CAH
t
AWD
t
AWD
t
CAC
t
AA
t
DH
t
CLZ
t
RAC
t
DH
t
DH
t
OE
t
CLZ
t
CAC
t
OE
t
CAC
t
OE
OUT
OUT
IN
IN
IN
t
OD
t
OD
t
DS
t
OD
t
DS
t
CLZ
t
AA
t
AA
t
WP
t
RAH
t
WP
t
WP
t
CWL
t
CWL
t
CWL
t
RWL
t
CAH
t
CRP
t
DS
IC41SV44052
IC41SV44054
16
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
HIDDEN REFRESH CYCLE
(1)
(
WE
= HIGH;
OE
= LOW)
CBR REFRESH CYCLE
(Addresses;
WE
,
OE
= DON'T CARE)
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS
Row
Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O
Open
Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don't Care
Don't Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case,
WE = LOW and OE = HIGH.
2. t
OFF
is referenced from rising edge of
RAS or CAS, whichever occurs last.
IC41SV44052
IC41SV44054
Integrated Circuit Solution Inc.
17
DR035-0B 7/31/2002
ORDERING INFORMATION
Commercial Range: -10


C to 70C
Voltage: 2.2V
Speed (ns)
Order Part No.
Package
70
IC41SV44052-70J
300mil SOJ
70
IC41SV44052-70T
300mil TSOP-2
70
IC41SV44052-70JG
300mil SOJ Pb-free
70
IC41SV44052-70TG
300mil TSOP-2 Pb-free
100
IC41SV44052-100J
300mil SOJ
100
IC41SV44052-100T
300mil TSOP-2
100
IC41SV44052-100JG
300mil SOJ Pb-free
100
IC41SV44052-100TG
300mil TSOP-2 Pb-free
Speed (ns)
Order Part No.
Package
70
IC41SV44054-70J
300mil SOJ
70
IC41SV44054-70T
300mil TSOP-2
70
IC41SV44054-70JG
300mil SOJ Pb-free
70
IC41SV44054-70TG
300mil TSOP-2 Pb-free
100
IC41SV44054-100J
300mil SOJ
100
IC41SV44054-100T
300mil TSOP-2
100
IC41SV44054-100JG
300mil SOJ Pb-free
100
IC41SV44054-100TG
300mil TSOP-2 Pb-free
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw