Integrated
Circuit
Systems, Inc.
ICS93V857-XXX
0693K--03/13/03
1
Block Diagram
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
Pin Configuration
48-Pin TSSOP & TVSOP
Recommended Application:
DDR Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum tolerant inputs
Auto PD when input signal removed
Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
Switching Characteristics:
Period jitter (>66MHz): <40ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS93V857-025/125/130
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S
T
U
P
N
I
S
T
U
P
T
U
O
e
t
a
t
S
L
L
P
D
D
V
A
#
D
P
T
N
I
_
K
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C
C
N
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L
C
T
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L
C
C
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C
T
T
U
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B
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T
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B
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Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD#
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
2
ICS93V857-XXX
0693K--03/13/03
Pin Descriptions
R
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This PLL Clock Buffer is designed for a V
DD
of 2.5V, AV
DD
of 2.5V and differential data input and output levels.
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV
DD
). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0C to 85C.
3
ICS93V857-XXX
0693K--03/13/03
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V
DD
+ 0.5V
Ambient Operating Temperature . . . . . . . . . . 0C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
I
= V
DD
or GND
5
A
Input Low Current
I
IL
V
I
= V
DD
or GND
5
A
I
DD2.5
C
L
= 0pf @ 100MHz
250
mA
I
DDPD
C
L
= 0pf
65
90
mA
Input Clamp Voltage
V
IK
V
DDQ
= 2.3V Iin = -18mA
-1.2
V
I
OH
= -1 mA
V
DD
- 0.1
2.45
V
I
OH
= -12 mA
1.7
2.10
V
I
OL
=1 mA
0.05
0.1
V
I
OL
=12 mA
0.35
0.6
V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
3
pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
3
pF
1
Guaranteed by design at 233MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage
V
OH
Low-level output voltage
V
OL
4
ICS93V857-XXX
0693K--03/13/03
Recommended Operating Condition (see note1)
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
DDQ
, A
VDD
2.3
2.5
2.7
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.4
V
DD
/2 - 0.18
V
PD#
-0.3
0.7
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
V
DD
/2 + 0.18
2.1
V
PD#
1.7
V
DD
+ 0.6
V
DC input signal voltage
(note 2)
V
IN
-0.3
V
DD
+ 0.3
V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
V
DD
+ 0.6
V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.7
V
DD
+ 0.6
V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15
V
DD
/2 + 0.15
V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2
V
DD
/2
V
DD
/2 + 0.2
V
High level output current
I
OH
-12
mA
Low level output current
I
OL
12
mA
High Impedance
Output Current
I
OZ
V
DD
=2.7V, V
OUT
=V
DD
or GND
0.1
10
mA
Operating free-air
temperature
T
A
0
85
C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage
V
IL
High level input voltage
V
IH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal must be crossing.
5
ICS93V857-XXX
0693K--03/13/03
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, were
the cycle (t
c
) decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
Timing Requirements
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
3
freq
op
2.5V+0.2V
33
233
MHz
Application Frequency
Range
3
freq
App
2.5V+0.2V
60
170
MHz
Input clock duty cycle
d
tin
40
60
%
CLK stabilization
T
STAB
100
s
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
t
PLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
t
PHL
1
CLK_IN to any output
5.5
ns
Output enable time
t
en
PD# to any output
5
ns
Output disable time
t
dis
PD# to any output
5
ns
Period jitter
t
jit (per)
66/100/125/133/167MHz
-40
40
ps
100 to <170MHz
-100
100
ps
170MHz to 233MHz
-120
50
ps
Input clock slew rate
t
sl(I)
1
4
v/ns
Output clock slew rate
t
sl(o)
66/100/133/167MHz
1
2
v/ns
Cycle to Cycle Jitter
1
t
cyc
-t
cyc
66/100/125/133/167MHz
60
ps
Phase error
t
(phase error)
4
-50
0
50
ps
Output to Output Skew
t
skew
40
60
ps
Rise Time, Fall Time
t
r
, t
f
Load = 120
/16pF
650
800
950
ps
t
jit(hper)
Half-period jitter
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