Integrated
Circuit
Systems, Inc.
ICS94225
0445B--08/01/03
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
AMD 750/760 style chipset
Output Features:
3 differential pair open drain CPU clocks (1.5V
external
pull-up; up to 150MHz achieviable through I
2
C)
2 - AGPCLK @ 3.3V
8 - PCI @3.3V, including 1 free running
1 - 48MHz @ 3.3V
1 - 24/48MHz @ 3.3V
2- REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable group skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
AMD-K7
TM
System Clock Chip
* Internal 120K pullup resistor on indicated inputs
** Internal 240K pullup resistor on indicated inputs
**FS0/REF0
**FS1/REF1
GNDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK0
VDDPCI
PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
VDDAGP
AGP0
AGP1
GNDAGP
VDD48
48MHz
SEL24_48#/24-48MHz
VDDREF
GNDSD
SDRAM_OUT
VDDSD
RESERVED
CPUCLKC2
CPUCLKT2
GNDCPU
CPUCLKC1
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
RESET#
VDD
GND
PCI_STOP#
CPU_STOP#
PD#
SPREAD#
FS2*
SDATA
SCLK
GND48
ICS94225
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDREF, GNDREF= REF, X1, X2
VDD, GND = PLL Core
0
0
0
133.33
33.33
66.67
0
0
1
95
31.67
63.33
0
1
0
100.99
33.66
67.33
0
1
1
115
38.33
76.67
1
0
0
100.7
33.57
67.13
1
0
1
103
34.33
68.67
1
1
0
105
35.00
70.00
1
1
1
110
36.67
73.33
PCI
AGP
FS2
FS1
FS0
CPU,
SDRAM
SEL24_48#
SDATA
SCLK
FS (2:0)
PD#
PCI_STOP#
CPU_STOP#
SPREAD#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM_OUT
PCICLK (6:0)
AGP (1:0)
PCICLK_F
2
7
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
2
ICS94225
0445B--08/01/03
Pin Descriptions
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General Description
The ICS94225 is a main clock synthesizer chip for AMD-K7 based systems with AMD 750/760 style chipsets. This
provides all clocks required for such a system.
The ICS94225 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
3
ICS94225
0445B--08/01/03
Byte 1: Reserved Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
1
1
0
F
E
R
6
3
2
1
z
H
M
8
4
/
z
H
M
4
2
5
2
2
1
0
B
S
U
4
0
2
1
1
P
G
A
3
9
1
1
0
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G
A
2
3
4
,
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4
1
2
T
/
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P
C
1
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4
,
9
3
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/
C
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L
C
U
P
C
0
7
3
,
6
3
1
0
T
/
C
K
L
C
U
P
C
Byte 4: Clock Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
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R
6
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1
6
K
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C
P
5
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5
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L
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C
P
4
4
1
1
4
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L
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C
P
3
3
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1
3
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L
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C
P
2
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1
1
2
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L
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C
P
1
0
1
1
1
K
L
C
I
C
P
0
8
1
0
K
L
C
I
C
P
Byte 5: PCI Clock Control Register
(1= enable, 0 = disable)
Byte 3: Reserved Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
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I
T
P
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R
C
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D
7
t
i
B
-
1
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d
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v
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s
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R
(
6
t
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B
-
1
)
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s
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R
(
5
t
i
B
-
1
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d
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s
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R
(
4
t
i
B
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1
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s
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R
(
3
t
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B
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1
)
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v
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s
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R
(
2
t
i
B
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1
)
d
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v
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s
e
R
(
1
t
i
B
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1
)
d
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v
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s
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R
(
0
t
i
B
-
1
)
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s
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R
(
T
I
B
#
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P
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P
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R
C
S
E
D
7
t
i
B
-
1
)
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v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
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v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
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v
r
e
s
e
R
(
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1
)
d
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v
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s
e
R
(
1
t
i
B
-
1
)
d
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v
r
e
s
e
R
(
0
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
ICS94225
0445B--08/01/03
Notes:
1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
2. PWD = Power-Up Default
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit
PWD
7
0
0
0
0
0
0
133.33
33.33
66.67
0
0
0
0
1
95
31.67
63.33
0
0
0
1
0
100.99
33.66
67.33
0
0
0
1
1
115
38.33
76.67
0
0
1
0
0
100.7
33.57
67.13
0
0
1
0
1
103
34.33
68.67
0
0
1
1
0
105
35.00
70.00
0
0
1
1
1
110
36.67
73.33
0
1
0
0
0
102
34.00
68.00
0
1
0
0
1
104
34.67
69.33
0
1
0
1
0
106
35.33
70.67
0
1
0
1
1
107
35.67
71.33
0
1
1
0
0
108
36.00
72.00
0
1
1
0
1
109
36.33
72.67
0
1
1
1
0
90
30.00
60.00
0
1
1
1
1
111
37.00
74.00
1
0
0
0
0
112
37.33
74.67
1
0
0
0
1
113
37.67
75.33
1
0
0
1
0
114
38.00
76.00
1
0
0
1
1
116
38.67
77.33
1
0
1
0
0
117
39.00
78.00
1
0
1
0
1
118
39.33
78.67
1
0
1
1
0
119
39.67
79.33
1
0
1
1
1
120
30.00
60.00
1
1
0
0
0
142
35.50
71.00
1
1
0
0
1
144
36.00
72.00
1
1
0
1
0
146
36.50
73.00
1
1
0
1
1
138
34.50
69.00
1
1
1
0
0
136
34.00
68.00
1
1
1
0
1
135
33.75
67.50
1
1
1
1
0
140
35.00
70.00
1
1
1
1
1
150
37.50
75.00
Description
Spread Spectrum enable (+/- 0.25% center spread) 0=OFF 1=ON
6:2
Bit 3
Bit 2
FS2
Bit 6
FS1
Bit 5
FS0
Bit 4
CPU,
SDRAM
PCI
0
0 - SDRAM_OUT Disable
1 - SDRAM_OUT Enable
1
AGP
0010
Note1
1
0 - Frequency is selected by hardware select, latched input;
Spread controlled by pin 29
1 - Frequency is selected by Bit (6:2); Spread controlled by Bit
0
5
ICS94225
0445B--08/01/03
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Notes:
1. PWD = Power on Default
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
d
e
v
r
e
s
e
R
6
t
i
B
0
d
e
v
r
e
s
e
R
5
t
i
B
0
d
e
v
r
e
s
e
R
4
t
i
B
0
d
e
v
r
e
s
e
R
3
t
i
B
1
d
e
v
r
e
s
e
R
2
t
i
B
0
d
e
v
r
e
s
e
R
1
t
i
B
0
d
e
v
r
e
s
e
R
0
t
i
B
0
d
e
v
r
e
s
e
R
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
D
I
r
o
d
n
e
V
6
t
i
B
0
D
I
r
o
d
n
e
V
5
t
i
B
1
D
I
r
o
d
n
e
V
4
t
i
B
X
D
I
n
o
i
s
i
v
e
R
3
t
i
B
X
D
I
n
o
i
s
i
v
e
R
2
t
i
B
X
D
I
n
o
i
s
i
v
e
R
1
t
i
B
X
D
I
n
o
i
s
i
v
e
R
0
t
i
B
X
D
I
n
o
i
s
i
v
e
R
Byte 11: VCO Frequency Control Register
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
0
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
X
6
t
i
B
r
e
d
i
v
i
D
F
E
R
5
t
i
B
X
5
t
i
B
r
e
d
i
v
i
D
F
E
R
4
t
i
B
X
4
t
i
B
r
e
d
i
v
i
D
F
E
R
3
t
i
B
X
3
t
i
B
r
e
d
i
v
i
D
F
E
R
2
t
i
B
X
2
t
i
B
r
e
d
i
v
i
D
F
E
R
1
t
i
B
X
1
t
i
B
r
e
d
i
v
i
D
F
E
R
0
t
i
B
X
0
t
i
B
r
e
d
i
v
i
D
F
E
R
Byte 12: VCO Frequency Control Register
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
8
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
X
7
t
i
B
r
e
d
i
v
i
D
O
C
V
5
t
i
B
X
6
t
i
B
r
e
d
i
v
i
D
O
C
V
4
t
i
B
X
5
t
i
B
r
e
d
i
v
i
D
O
C
V
3
t
i
B
X
4
t
i
B
r
e
d
i
v
i
D
O
C
V
2
t
i
B
X
3
t
i
B
r
e
d
i
v
i
D
O
C
V
1
t
i
B
X
2
t
i
B
r
e
d
i
v
i
D
O
C
V
0
t
i
B
X
1
t
i
B
r
e
d
i
v
i
D
O
C
V
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
q
e
r
f
2
1
&
1
1
B
=
1
/
q
e
r
f
0
B
/
w
H
=
0
6
t
i
B
0
e
l
b
a
n
e
=
1
/
e
l
b
a
s
i
d
=
0
e
l
b
a
n
E
D
W
5
t
i
B
0
m
r
a
l
a
=
1
/
l
a
m
r
o
n
=
0
s
u
t
a
t
S
D
W
4
t
i
B
1
2
t
i
b
0
e
t
y
B
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
3
t
i
B
0
3
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
2
t
i
B
0
2
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
1
t
i
B
0
1
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
0
t
i
B
0
0
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
Byte 9: Watchdog Timer Count Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
e
s
e
h
t
f
o
n
o
i
t
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
s
m
1
r
o
s
m
0
9
2
o
t
d
n
o
p
s
e
r
r
o
c
s
t
i
b
8
e
r
o
f
e
b
t
i
a
w
l
l
i
w
r
e
m
i
t
g
o
d
h
c
t
a
w
e
h
t
e
h
t
t
e
s
e
r
d
n
a
e
d
o
m
m
r
a
l
a
o
t
s
e
o
g
t
i
t
l
u
a
f
e
D
.
g
n
i
t
t
e
s
e
f
a
s
e
h
t
o
t
y
c
n
e
u
q
e
r
f
.
s
m
0
9
2
s
i
p
u
r
e
w
o
p
t
a
6
t
i
B
0
5
t
i
B
0
4
t
i
B
0
3
t
i
B
0
2
t
i
B
0
1
t
i
B
0
0
t
i
B
0
6
ICS94225
0445B--08/01/03
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
7
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
6
t
i
B
X
6
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
5
t
i
B
X
5
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
4
t
i
B
X
4
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
3
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
2
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
0
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
1
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
9
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
l
o
r
t
n
o
C
w
e
k
S
2
T
/
2
C
K
L
C
U
P
C
6
t
i
B
X
5
t
i
B
X
4
t
i
B
X
3
t
i
B
X
l
o
r
t
n
o
C
w
e
k
S
F
_
K
L
C
I
C
P
2
t
i
B
X
1
t
i
B
X
0
t
i
B
X
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
0
T
K
L
C
U
P
C
6
t
i
B
X
0
C
K
L
C
U
P
C
5
t
i
B
X
1
T
K
L
C
U
P
C
4
t
i
B
X
1
C
K
L
C
U
P
C
3
t
i
B
X
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
)
0
:
2
(
P
G
A
2
t
i
B
X
1
t
i
B
X
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
)
0
:
1
(
6
6
V
3
0
t
i
B
X
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
0
:
3
(
I
C
P
6
t
i
B
X
5
t
i
B
X
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
)
4
:
6
(
I
C
P
4
t
i
B
X
3
t
i
B
X
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
2
t
i
B
X
1
t
i
B
X
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
4
2
0
t
i
B
X
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I
2
C (Byte 0 bit [1:7]) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
l
o
r
t
n
o
C
w
e
k
S
)
0
:
6
(
K
L
C
I
C
P
6
t
i
B
X
5
t
i
B
X
4
t
i
B
X
3
t
i
B
X
l
o
r
t
n
o
C
w
e
k
S
)
0
:
3
(
P
G
A
2
t
i
B
X
1
t
i
B
X
0
t
i
B
X
7
ICS94225
0445B--08/01/03
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)
-0.5
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO
frequency.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19
H
) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
Byte 19: Reserved Register
Note:
Byte 19 and 20 are reserved registers, these
are unused registers writing to these registers
will not affect device performance or
functinality.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
Byte 20: Reserved Register
8
ICS94225
0445B--08/01/03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
A
Input Low Current
I
IL1
V
IN
=0 V; Inputs with no pull-up
resistors
-5
I
IL2
V
IN
=0 V; Inputs with pull-up
resistors
-200
I
DD3.3OP66
C
L
=0 pF; Select@ 66MHz
87
I
DD3.3OP100
C
L
=0 pF; Select@ 100MHz
91
I
DD3.3OP133
C
L
=0 pF; Select@ 133MHz
104
Power Down
PD
3.25
5
mA
Input frequency
Fi
V
DD
= 3.3 V
12
14.318
16
MHz
C
IN
Logic Inputs
5
pF
Input Capacitance
1
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
T
STAB
From V
DD
= 3.3 V to 1% target
Freq.
3
ms
t
CPU-PCI
V
T
= 50% to 1.5V
1
2.85
4
ns
180
mA
mA
1
Guaranteed by design, not 100% tested in production.
Input Low Current
Supply Current
9
ICS94225
0445B--08/01/03
Electrical Characteristics - USB, REF(1:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, VOH = 2.4 V
0.98
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, VOL = 0.4 V
0.77
4
ns
Duty Cycle
1
d
t5
VT = 1.5V
45
54
57
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
VT = 1.5V
471
1100
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
Z
0
V
O
= V
X
Output High Voltage
V
OH2B
1
1.2
V
Output Low Voltage
V
OL2B
0.4
V
Output Low Current
I
OL2B
V
OL
= 0.3 V
18
mA
Rise Time
1
t
r2B
V
OL
= 0.3 V, V
OH
= 1.2 V
0.9
ns
Fall Time
1
tf2B
V
OH
= 1.2 V, V
OL
= 0.3 V
0.9
ns
Differential voltage-AC
1
V
DIF
Note 2
0.4
V
Differential voltage-DC
1
V
DIF
Note 2
0.2
V
Differential Crossover
V
X
Note 3
550
1100
mV
Duty Cycle
1
d
t2B
V
T
= 50%
45
51
55
%
Skew
1
t
sk2B
V
T
= 50%
46
200
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= VX
86
250
ps
Jitter, Absolute
1
t
jabs2B
V
T
= 50%
-250
250
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
3 - Vpullup
(external)
= 1.5V, Min = Vpullup
(external)
/2-150mV; Max=(Vpullup
(external)
/2)+150mV
Vpu
+0.6
Termination to Vpull-up(external)
2 - V
DIF
specifies the minimum input differential voltages (V
TR
-V
CP
) required for switching, where V
TR
is the "true"
input level and V
CP
is the "complement" input level.
10
ICS94225
0445B--08/01/03
Electrical Characteristics - PCICLK_F, PCICLK(6:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -11 mA
2.6
V
Output Low Voltage
V
OL5
I
OL
= 9.4 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-16
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
19
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, VOH = 2.4 V
1.8
2
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, VOL = 0.4 V
1.8
2
ns
Duty Cycle
1
d
t5
V
T
= 1.5V
45
51.7
55
%
Skew
1
t
sk2B
V
T
= 1.5V
175
200
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5V
122
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F, PCICLK(6:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -11 mA
2.6
V
Output Low Voltage
V
OL5
I
OL
= 9.4 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-16
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
19
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, VOH = 2.4 V
1.8
2
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, VOL = 0.4 V
1.8
2
ns
Duty Cycle
1
d
t5
V
T
= 1.5V
45
51.7
55
%
Skew
1
t
sk2B
V
T
= 1.5V
175
200
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.5V
122
500
ps
1
Guaranteed by design, not 100% tested in production.
11
ICS94225
0445B--08/01/03
Electrical Characteristics - AGP(1:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH5
I
OH
= -18 mA
2.6
V
Output Low Voltage
V
OL5
I
OL
= 1.8 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-16
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
19
mA
Rise Time
1
t
r5
V
OL
= 0.4 V, VOH = 2.4 V
1.05
1.6
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, VOL = 0.4 V
1.27
1.6
ns
Duty Cycle
1
d
t5
V
T
= 50%
45
50.4
55
%
Skew
1
(window)
T
sk
1
V
T
= 50%
12
200
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 50%
268
500
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
V
OH3
I
OH
= -11 mA
2
V
Output Low Voltage
V
OL3
I
OL
= 11 mA
0.4
V
Output High Current
I
OH3
V
OH
= 2.0 V
-12
mA
Output Low Current
I
OL3
V
OL
= 0.8 V
12
mA
Rise Time
1
t
r3
V
OL
= 0.4 V, VOH = 2.4 V@100MHz
0.83
1.6
ns
Fall Time
1
t
f3
V
OH
= 2.4 V, VOL = 0.4 V@100MHz
0.71
1.6
ns
Duty Cycle
1
d
t3
V
T
= 50%
45
50.8
55
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc3B
V
T
= 50% @ 100MHz
240
250
ps
1
Guaranteed by design, not 100% tested in production.
12
ICS94225
0445B--08/01/03
General I
2
C serial interface information for the ICS94225
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 12
H
has been written to B6
Byte18
ACK
If 13
H
has been written to B6
Byte 19
ACK
If 14
H
has been written to B6
Byte 20
ACK
Stop Bit
How to Read:
13
ICS94225
0445B--08/01/03
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94225
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Functionality &
Frequency Select
Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte
description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte
description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
See individual
byte
description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
10
H
Watchdog Control
Registers
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
VCO Control Selection
Bit
10 Bit [7]
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
Spread Spectrum
Control Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte
0 configuration
Group Skews Control
Registers
15-16
Increment or decrement the group
skew amount as compared to the
initial skew.
See individual
byte
description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the
output rise and fall time.
See individual
byte
description
14
ICS94225
0445B--08/01/03
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
15
ICS94225
0445B--08/01/03
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power
operation. CPU_STOP# is synchronized by the ICS94225. All other clocks will continue to run while the CPUCLKs
clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than
4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS94225.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCICLK
CPUCLKT
CPUCLKC
PD# (High)
CPU_STOP#
INTERNAL
CPUCLK
16
ICS94225
0445B--08/01/03
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94225. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94225 internally. PCICLK clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94225 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94225.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PWR_DWN#
PCICLK
(External)
PCI_STOP#
17
ICS94225
0445B--08/01/03
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94225 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
PD#
18
ICS94225
0445B--08/01/03
Ordering Information
ICS94225yF-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
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