Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Pin Configuration

Recommended Application:

CK409 clock, Intel Yellow Cover part

Output Features:

3 - 0.7V current-mode differential CPU pairs

1 - 0.7V current-mode differential SRC pair

7 - PCI (33MHz)

3 - PCICLK_F, (33MHz) free-running

1 - USB, 48MHz

1 - DOT, 48MHz

2 - REF, 14.318MHz

4 - 3V66, 66.66MHz

1 - VCH/3V66, selectable 48MHz or 66MHz

Key Specifications:

CPU/SRC outputs cycle-cycle jitter < 125ps

3V66 outputs cycle-cycle jitter < 250ps

PCI outputs cycle-cycle jitter < 250ps

CPU outputs skew: < 100ps

+/- 300ppm frequency accuracy on CPU & SRC clocks

Programmable Timing Control HubTM for Next Gen P

TM processor

Functionality

Features/Benefits:

Supports tight ppm accuracy clocks for Serial-ATA

Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread

Supports CPU clks up to 400MHz in test mode

Uses external 14.318MHz crystal

Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

56-pin SSOP & TSSOP

REF0

56 FS_B

REF1

55 VDDA

VDDREF

54 GNDA

53 GND

52 IREF

GND

51 FS_A

PCICLK_F0

50 CPU_STOP#

PCICLK_F1

49 PCI_STOP#

PCICLK_F2

48 VDDCPU

VDDPCI 10

47 CPUCLKT2

GND 11

46 CPUCLKC2

PCICLK0 12

45 GND

PCICLK1 13

44 CPUCLKT1

PCICLK2 14

43 CPUCLKC1

PCICLK3 15

42 VDDCPU

VDDPCI 16

41 CPUCLKT0

GND 17

40 CPUCLKC0

PCICLK4 18

39 GND

PCICLK5 19

38 SRCCLKT

PCICLK6 20

37 SRCCLKC

PD# 21

36 VDD

3V66_0 22

35 Vtt_PWRGD#

3V66_1 23

34 VDD48

VDD3V66 24

33 GND

GND 25

32 48MHz_DOT

3V66_2 26

31 48MHz_USB

3V66_3 27

30 SDATA

SCLK 28

29 3V66_4/VCH

ICS952623

B6b5 FS_A FS_B

CPU
MHz

SRC
MHz

3V66

MHz

PCI

MHz

REF

MHz

SB/DOT

MHz

100

100/200 66.66 33.33 14.318

48.00

MID Ref/N

Ref/N

200

100/200 66.66 33.33 14.318

48.00

133

100/200 66.66 33.33 14.318

48.00

166

100/200 66.66 33.33 14.318

48.00

MID

Hi-Z

200

100/200 66.66 33.33 14.318

48.00

400

100/200 66.66 33.33 14.318

48.00

266

100/200 66.66 33.33 14.318

48.00

333

100/200 66.66 33.33 14.318

48.00

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Pin Description

PIN

PIN NAME

PIN TYPE

DESCRIPTION

REF0

OUT

14.318 MHz reference clock.

REF1

OUT

14.318 MHz reference clock.

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

Crystal input, Nominally 14.318MHz.

OUT

Crystal output, Nominally 14.318MHz

GND

PWR

Ground pin.

PCICLK_F0

OUT

Free running PCI clock not affected by PCI_STOP# .

PCICLK_F1

OUT

Free running PCI clock not affected by PCI_STOP# .

PCICLK_F2

OUT

Free running PCI clock not affected by PCI_STOP# .

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

GND

PWR

Ground pin.

PCICLK0

OUT

PCI clock output.

PCICLK1

OUT

PCI clock output.

PCICLK2

OUT

PCI clock output.

PCICLK3

OUT

PCI clock output.

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

GND

PWR

Ground pin.

PCICLK4

OUT

PCI clock output.

PCICLK5

OUT

PCI clock output.

PCICLK6

OUT

PCI clock output.

PD#

Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 1.8ms. Internal pull-up of 150K nominal.

3V66_0

OUT

3.3V 66.66MHz clock output

3V66_1

OUT

3.3V 66.66MHz clock output

VDD3V66

PWR

Power pin for the 3V66 clocks.

GND

PWR

Ground pin.

3V66_2

OUT

3.3V 66.66MHz clock output

3V66_3

OUT

3.3V 66.66MHz clock output

SCLK

Clock pin of I2C circuitry 5V tolerant

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Pin Description (Continued)

PIN

PIN NAME

PIN TYPE

DESCRIPTION

3V66_4/VCH

OUT

66.66MHz clock output for AGP support. AGP-PCI should be
aligned with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

48MHz_USB

OUT

48MHz clock output.

48MHz_DOT

OUT

48MHz clock output.

GND

PWR

Ground pin.

VDD48

PWR

Power for 48MHz output buffers and fixed PLL core.

Vtt_PWRGD#

This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.

VDD

PWR

Power supply for SRC clocks, nominal 3.3V

SRCCLKC

OUT

Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.

SRCCLKT

OUT

True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.

GND

PWR

Ground pin.

CPUCLKC0

OUT

"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.

CPUCLKT0

OUT

"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

CPUCLKC1

OUT

"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.

CPUCLKT1

OUT

"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.

GND

PWR

Ground pin.

CPUCLKC2

OUT

"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.

CPUCLKT2

OUT

"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.

VDDCPU

PWR

Supply for CPU clocks, 3.3V nominal

PCI_STOP#

Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at
logic 0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.

CPU_STOP#

Stops all CPUCLK besides the free running clocks. Internal pull-up
of 150K nominal

FS_A

Frequency select pin, see Frequency table for functionality

IREF

OUT

IREF establishes the reference current for the CPUCLK pairs. A
fixed precision resistor tied to ground is required to establish the
appropriate current.

GND

PWR

Ground pin.

GNDA

PWR

Ground pin for core.

VDDA

PWR

3.3V power for the PLL core.

FS_B

Frequency select pin, see Frequency table for functionality

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

ICS952623 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS952623 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.

General Description

Block Diagram

I REF

PLL2

Frequency

Dividers

Programmable

Spread

PLL1

Programmable

Frequency

Dividers

STOP

Logic

48MHz, USB, DOT

X1
X2

XTAL

SDATA

SCLK

CPU_STOP#

PCI_STOP#

Vtt_PWRGD#

PD#

FS_A

FS_B

Control

Logic

REF (1:0)

CPUCLKT (2:0)

CPUCLKC (2:0)

SRCCLKT0

SRCCLKC0

3V66(4:0)

PCICLK (6:0)

PCICLKF (2:0)

Power Groups

VDD

GND

Xtal, Ref

3V66 [0:3]

10,16

11,17

PCICLK outputs

SRCCLK outputs

Master clock, CPU Analog

48MHz, PLL

N/A

IREF

48, 42

CPUCLK clocks

Description

Pin Number

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

+ 0.5V

VDD_In

3.3V Logic Input Supply Voltage

GND - 0.5

+ 0.5V

Storage Temperature

-65

150

Tambient

Ambient Operating Temp

°C

Tcase Case

Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

Electrical Characteristics - Input/Supply/Common Output Parameters

= 0 - 70°C; Supply Voltage V

= 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

3.3 V +/-5%

+ 0.3

Input MID Voltage

MID

3.3 V +/-5%

1.8

Input Low Voltage

3.3 V +/-5%

- 0.3

0.8

Input High Current

= V

-5

IL1

= 0 V; Inputs with no pull-

up resistors

-5

IL2

= 0 V; Inputs with pull-up

resistors

-200

Operating Supply Current

DD3.3OP

Full Active, C

= Full load;

350

all diff pairs driven

all differential pairs tri-stated

Input Frequency

= 3.3 V

14.31818

MHz

Pin Inductance

Logic Inputs

OUT

Output pin capacitance

INX

X1 & X2 pins

Clk Stabilization

1,2

STAB

From V

Power-Up or de-

assertion of PD# to 1st clock

1.8

1,2

Modulation Frequency

Triangular Modulation

kHz

Tdrive_SRC

SRC output enable after

PCI_Stop# de-assertion

Tdrive_PD#

CPU output enable after

PD# de-assertion

300

Tfall_Pd#

PD# fall time of

Trise_Pd#

PD# rise time of

Tdrive_CPU_Stop#

CPU output enable after

CPU_Stop# de-assertion

Tfall_CPU_Stop#

PD# fall time of

Trise_CPU_Stop#

PD# rise time of

Guaranteed by design, not 100% tested in production.

See timing diagrams for timing requirements.

DD3.3PD

Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet

ppm frequency accuracy on PLL outputs.

Input Capacitance

Input Low Current

Powerdown Current

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair

= 0 - 70°C; V

= 3.3 V +/-5%; C

=2pF

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Current Source Output

Impedance

= V

3000

Voltage High

VHigh

660

850

Voltage Low

VLow

-150

150

Max Voltage

Vovs

1150

Min Voltage

Vuds

-300

Crossing Voltage (abs)

Vcross(abs)

250

550

Crossing Voltage (var)

d-Vcross

Variation of crossing over all

edges

140

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2

200MHz nominal

4.9985

5.0015

200MHz spread

4.9985

5.0266

166.66MHz nominal

5.9982

6.0018

166.66MHz spread

5.9982

6.0320

133.33MHz nominal

7.4978

7.5023

133.33MHz spread

7.4978

5.4000

100.00MHz nominal

9.9970

10.0030

100.00MHz spread

9.9970

10.0533

200MHz nominal

4.8735

1,2

166.66MHz nominal/spread

5.8732

1,2

133.33MHz nominal/spread

7.3728

1,2

100.00MHz nominal/spread

9.8720

1,2

Rise Time

= 0.175V, V

= 0.525V

175

700

Fall Time

= 0.525V V

= 0.175V

175

700

Rise Time Variation

d-t

125

Fall Time Variation

d-t

125

Duty Cycle

Measurement from differential

wavefrom

Skew t

sk3

= 50%

100

Jitter, Cycle to cycle

jcyc-cyc

Measurement from differential

wavefrom

125

Guaranteed by design, not 100% tested in production.

SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.

Statistical measurement on

single ended signal using

oscilloscope math function.

Measurement on single ended

signal using absolute value.

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at

14.31818MHz

Tperiod

Average period

Absolute min period

absmin

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Electrical Characteristics - 3V66 Mode: 3V66 [4:0]

= 0 - 70°C; V

= 3.3 V +/-5%; C

= 10-30 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2

66.66MHz output nominal

14.9955

15.0045

66.66MHz output spread

14.9955

15.0799

Output High Voltage

= -1 mA

2.4

Output Low Voltage

= 1 mA

0.55

@ MIN = 1.0 V

-33

@ MAX = 3.135 V

-33

@ MIN = 1.95 V

@ MAX = 0.4 V

Edge Rate

Rising edge rate

V/ns

Edge Rate

Falling edge rate

V/ns

Rise Time

= 0.4 V, V

= 2.4 V

0.5

Fall Time

= 2.4 V, V

= 0.4 V

0.5

Duty Cycle

= 1.5 V

Skew t

sk1

= 1.5 V

250

Jitter

jcyc-cyc

= 1.5 V 3V66

250

Guaranteed by design, not 100% tested in production.

Clock period

period

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is

at 14.31818MHz

Output High Current

Output Low Current

Electrical Characteristics - PCICLK/PCICLK_F

= 0 - 70°C; V

= 3.3 V +/-5%; C

= 10-30 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2

33.33MHz output nominal

29.9910

30.0090

33.33MHz output spread

29.9910

30.1598

Output High Voltage

= -1 mA

2.4

Output Low Voltage

= 1 mA

0.55

@MIN = 1.0 V

-33

@ MAX = 3.135 V

-33

@ MIN = 1.95 V

@ MAX = 0.4 V

Edge Rate

Rising edge rate

V/ns

Edge Rate

Falling edge rate

V/ns

Rise Time

= 0.4 V, V

= 2.4 V

0.5

Fall Time

= 2.4 V, V

= 0.4 V

0.5

Duty Cycle

= 1.5 V

Skew t

sk1

= 1.5 V

500

Jitter

jcyc-cyc

= 1.5 V 3V66

250

Guaranteed by design, not 100% tested in production.

Clock period

period

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref

output is at 14.31818MHz

Output High Current

Output Low Current

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Long Accuracy

ppm

see Tperiod min-max

values

-200

200

ppm

1,2

Clock period

period

48MHz output nominal

20.8257

20.8340

Output High Voltage

= -1 mA

2.4

Output Low Voltage

= 1 mA

0.55

@ MIN = 1.0 V

-33

@ MAX = 3.135 V

-33

@ MIN = 1.95 V

@ MAX = 0.4 V

Edge Rate

Rising edge rate

V/ns

Edge Rate

Falling edge rate

V/ns

Rise Time

= 0.4 V, V

= 2.4 V

0.5

Fall Time

= 2.4 V, V

= 0.4 V

0.5

Duty Cycle

= 1.5 V

Long Term Jitter

125us period jitter

(8kHz frequency

modulation amplitude)

Guaranteed by design, not 100% tested in production.

= 0 - 70°C; V

= 3.3 V +/-5%; C

= 5-10 pF (unless otherwise specified)

Electrical Characteristics - 48MHz DOT Clock

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref

output is at 14.31818MHz

Output High Current

Output Low Current

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Electrical Characteristics - VCH, 48MHz, USB

= 0 - 70°C; V

= 3.3 V +/-5%; C

= 10-20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS Notes

Long Accuracy

ppm

see Tperiod min-max values

-200

200

ppm

1,2

Clock period

period

48MHz output nominal

20.8257

20.8340

Output High Voltage

= -1 mA

2.4

Output Low Voltage

= 1 mA

0.55

@ MIN = 1.0 V

-33

@ MAX = 3.135 V

-33

@MIN = 1.95 V

@ MAX = 0.4 V

Edge Rate

Rising edge rate

V/ns

Edge Rate

Falling edge rate

V/ns

Rise Time

= 0.4 V, V

= 2.4 V

Fall Time

= 2.4 V, V

= 0.4 V

Duty Cycle

= 1.5 V

Long Term Jitter

125us period jitter

(8kHz frequency modulation

amplitude)

Guaranteed by design, not 100% tested in production.

Output Low Current

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref

output is at 14.31818MHz

Output High Current

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Electrical Characteristics - REF-14.318MHz

= 0 - 70°C; V

= 3.3 V +/-5%; C

= 10-20 pF (unless otherwise specified)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

Clock period

period

14.318MHz output nominal

69.8270

69.8550

Output High Voltage

= -1 mA

2.4

Output Low Voltage

= 1 mA

0.4

Output High Current

@MIN = 1.0 V,

@MAX = 3.135 V

-29

-23

Output Low Current

@MIN = 1.95 V,

@MAX = 0.4 V

Rise Time

= 0.4 V, V

= 2.4 V

Fall Time

= 2.4 V, V

= 0.4 V

Skew

sk1

= 1.5 V

500

Duty Cycle

= 1.5 V

Jitter

jcyc-cyc

= 1.5 V

1000

Guaranteed by design, not 100% tested in production.

Group to Group Skews at Common Transition Edges

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

3V66 to PCI

3V66-PCI

3V66 (4:0) leads 33MHz PCI

1.50

3.50

DOT-USB

DOT_USB

180 degrees out of phase

0.00

1.00

DOT-VCH

DOT_VCH

in phase

0.00

1.00

Integrated
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Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

C Table: Read-Back Register

Pin #

Name

Control Function

Type

PWD

Bit 7

RESERVED

Bit 6

RESERVED

Bit 5

RESERVED

Bit 4

RESERVED

Bit 3

PCI_STOP#

PCI STOP# Read

Back

Bit 2

CPU_STOP#

CPU STOP Read

Back

Bit 1

FSB

Freq Select 1 Read

Back

Bit 0

FSA

Freq Select 0 Read

Back

C Table: Spreading and Device Behavior Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

SRC/SRC#

SRC Free-Running

Control

FREE-RUN

STOPPABLE

Bit 6

SRC Output

Control

Disable

Enable

Bit 5

CPUT2/CPUC2

FREE-RUN

STOPPABLE

Bit 4

CPUT1/CPUC1

FREE-RUN

STOPPABLE

Bit 3

CPUT0/CPUC0

FREE-RUN

STOPPABLE

Bit 2

CPUT2/CPUC2

Output Control

Disable

Enable

Bit 1

CPUT1/CPUC1

Output Control

Disable

Enable

Bit 0

CPUT0/CPUC0

Output Enable

Disable

Enable

C Table: Output Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

SRC_PD#

Drive Mode

0: Driven in PD#

Driven

Hi-Z

Bit 6

SRC_Stop#

Drive Mode

0: Driven in

PCI_Stop#

Driven

Hi-Z

Bit 5

CPUT2_PD# Drive

Mode

Driven

Hi-Z

Bit 4

CPUT1_PD# Drive

Mode

Driven

Hi-Z

Bit 3

CPUT0_PD# Drive

Mode

Driven

Hi-Z

Bit 2

CPUT2_Stop Drive

Mode

Driven

Hi-Z

Bit 1

CPUT1_Stop Drive

Mode

Driven

Hi-Z

Bit 0

CPUT0_Stop Drive

Mode

Driven

Hi-Z

RESERVED

0:driven when stopped

1: Tri-stated

0:driven in PD#

1: Tri-stated

READBACK

READBACK of CPU(2:0)

Frequency

READBACK

RESERVED
RESERVED

RESERVED

Byte 0

-
-
-

Byte 1

37,38

46,47

43,44
40,41

Byte 2

37,38

CPU FREE-RUNNING

CONTROL

43,44
40,41

46,47

43,44

40,41

46,47

43,44

40,41

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

C Table: Output Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

PCI_Stop#

PCI_Stop# Control

0:all stoppable PCI

are stopped

Enable

Disable

Bit 6

PCICLK6

Output Control

Disable

Enable

Bit 5

PCICLK5

Output Control

Disable

Enable

Bit 4

PCICLK4

Output Control

Disable

Enable

Bit 3

PCICLK3

Output Control

Disable

Enable

Bit 2

PCICLK2

Output Control

Disable

Enable

Bit 1

PCICLK1

Output Control

Disable

Enable

Bit 0

PCICLK0

Output Control

Disable

Enable

C Table: Output Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

48MHz_USB

2x output drive

0=2x drive

2x drive

normal

Bit 6

48MHz_USB

Output Control

Disable

Enable

Bit 5

PCIF2

FREE-RUN

STOPPABLE

Bit 4

PCIF1

FREE-RUN

STOPPABLE

Bit 3

PCIF0

FREE-RUN

STOPPABLE

Bit 2

PCICLK_F2

Output Control

Disable

Enable

Bit 1

PCICLK_F1

Output Control

Disable

Enable

Bit 0

PCICLK_F0

Output Control

Disable

Enable

C Table: Output Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

48MHZ_DOT

Output Control

Disable

Enable

Bit 6

RESERVED

Bit 5

3V66_4/VCH

Select

Output Select

3V66

VCH

Bit 4

3V66_4/VCH

Output Control

Disable

Enable

Bit 3

3V66_3

Output Control

Disable

Enable

Bit 2

3V66_2

Output Control

Disable

Enable

Bit 1

3V66_1

Output Control

Disable

Enable

Bit 0

3V66_0

Output Control

Disable

Enable

Byte 4

9
8

PCI FREE-RUN NING

CONTROL

Byte 3

7,8,9,12,13,14,15,

18,19,20,37,38,

20
19
18
15
14

29
27
26
23

13
12

Byte 5

9
8
7

Integrated
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ICS952623

Advance Information

0758--02/08/05

C Table: Output Control and Fix Frequency Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Test Clock Mode

Disable

Enable

Bit 6

RESERVED

Bit 5

RESERVED

FS_A and FS_B

Operation

Normal

Test Mode

Bit 4

RESERVED

SRC Frequency

Select

100MHz

200MHz

Bit 3

Spread Type

Down/Center

Down

Center

Bit 2

Spread Spectrum Mode

Spread

OFF

Spread

Bit 1

REF1

Output Control

Disable

Enable

Bit 0

REF0

Output Control

Disable

Enable

C Table: Vendor & Revision ID Register

Pin #

Name

Control Function

Type

PWD

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

C Table: Byte Count Register

Pin #

Name

Control Function

Type

PWD

Bit 7

BC7

Bit 6

BC6

Bit 5

BC5

Bit 4

BC4

Bit 3

BC3

Bit 2

BC2

Bit 1

BC1

Bit 0

BC0

1,2,7,8,9,12,13,14,

15,18,19,20,22,23,2
6,27,29,31,32,37,38

,40,41,43,44,46,47

40,41,43,44,46,47

Byte 6

2
1

37,38

7,8,9,12,13,14,15,1

8,19,20,22,23,26,27

,29,31,32,37,38,40,

41,43,44,46,47

Byte 7

REVISION ID

-
-
-
-

VENDOR ID

-
-
-

Byte 8

Writing to this register

will configure how

many bytes will be

read back, default is

= 8 bytes.

-
-
-
-
-
-
-

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ICS952623

Advance Information

0758--02/08/05

C Table: Overclocking Output Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Over Clocking

1: over-clk

0: normal mode

Bit 2

Over Clocking

Bit 1

Over Clocking

Bit 0

Reserved

C Table: VCO Control Select Bit Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Programming ENABLE

Enables prograaming

bytes 11-14

DISABLED

ENABLED

Bit 6

RESERVED

Bit 5

RESERVED

Bit 4

RESERVED

Bit 3

RESERVED

Bit 2

RESERVED

Bit 1

RESERVED

Bit 0

RESERVED

C Table: VCO Frequency Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

N Div8

N Divider Bit 8

Bit 6

M Div6

Bit 5

M Div5

Bit 4

M Div4

Bit 3

M Div3

Bit 2

M Div2

Bit 1

M Div1

Bit 0

M Div0

Byte 10

-
-
-
-
-
-

The decimal

representation of M

Div (6:0) is equal to

reference divider

value. Default at

power up = latch-in or

Byte 0 Rom table.

Byte 11

Byte 9

See over clocking per bit 1

and 2

-
-
-
-

00= +15%, 01 = +20%

10= +5%, 11= +10%

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

C Table: VCO Frequency Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

N Div7

Bit 6

N Div6

Bit 5

N Div5

Bit 4

N Div4

Bit 3

N Div3

Bit 2

N Div2

Bit 1

N Div1

Bit 0

N Div0

C Table: Spread Spectrum Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

SSP7

Bit 6

SSP6

Bit 5

SSP5

Bit 4

SSP4

Bit 3

SSP3

Bit 2

SSP2

Bit 1

SSP1

Bit 0

SSP0

C Table: Spread Spectrum Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Reserved

Bit 6

Reserved

Bit 5

SSP13

Bit 4

SSP12

Bit 3

SSP11

Bit 2

SSP10

Bit 1

SSP9

Bit 0

SSP8

Byte 12

The decimal

representation of N

Div (8:0) is equal to

VCO divider value.

Default at power up =

latch-in or Byte 0 Rom

table.

-
-
-
-
-
-

Byte 13

These Spread

Spectrum bits will

program the spread

pecentage. It is

recommended to use

ICS Spread % table

for spread

programming.

-
-
-
-
-
-

It is recommended to

use ICS Spread %

table for spread

programming.

-
-
-
-
-

Byte 14

-
-

Integrated
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Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.

PCI Stop Functionality

The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.

PCI_STOP#

Tsu

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# Assertion (transition from '1' to '0')

The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.

PCI_STOP#

Tsu

Tdrive_SRC

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# - De-assertion

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ICS952623

Advance Information

0758--02/08/05

The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.

CPU_STOP# Functionality

Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.

CPU_STOP#

CPU

CPU#

CPU_STOP# - Assertion (transition from '1' to '0')

With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.

CPU_Stop#

Tdrive_CPU_Stop, 10nS >200mV

CPU

CPU#

CPU Internal

CPU_STOP# - De-assertion (transition from '0' to '1')

Integrated
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Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.

PD#, Power Down

Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.

PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.

PWRDWN#

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC#, 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

PD# Assertion

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Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300

µs of PD# deassertion.

PWRDWN#

Tstable

<1.8mS

Tdrive_PwrDwn#

<300

µS, >200mV

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC# 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

PD# De-assertion

The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.

3V66

3V66_4/VCH

DOT_48

7.49nS min

3V66_4/VCH Pin Functionality

Integrated
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Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.

}

[

}

[

}

[

}

[

}

[

Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address

Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address

Differential Clock Tristate

Integrated
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Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.

CPU_Stop = Driven, CPU_Pwrdwn = Driven

CPU_Stop#

1.8mS

PD#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")

CPU Clock Tristate Timing

CPU_Stop = Tristate, CPU_Pwrdwn = Driven

CPU_Stop#

1.8mS

PD#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.

Integrated
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ICS952623

Advance Information

0758--02/08/05

CPU_Stop = Driven, CPU_Pwrdwn = Tristate

CPU_Stop#

1.8mS

PWRDWN#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.

CPU_Stop = Tristate, CPU_Pwrdwn = Tristate

CPU_Stop#

1.8mS

PWRDWN#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.

Integrated
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ICS952623

Advance Information

0758--02/08/05

The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.

SRC_Stop = Driven, SRC_Pwrdwn = Driven

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

1 PCI

clock max

Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")

SRC Clock Tristate Timing

SRC_Stop = Tristate, Pwrdwn = Tristate

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

1 PCI

clock max

Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.

Integrated
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ICS952623

Advance Information

0758--02/08/05

PCI_STOP Asserted

SRC_Stop = Tristate, SRC_Pwrdwn = Tristate

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.

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ICS952623

Advance Information

0758--02/08/05

Fig. 1

Shared Pin Operation -
Input/Output Pins

The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.

To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)
resistor is used to provide both the solid CMOS programming
voltage needed during the power-up programming period and to
provide an insignificant load on the output clock during the
subsequent operating period.

Via to
VDD

Clock trace to load

Series Term. Res.

Programming
Header

Via to Gnd

Device
Pad

8.2K

Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.

Integrated
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ICS952623

Advance Information

0758--02/08/05

Ordering Information

ICS952623yFT

Designation for tape and reel packaging

Package Type
F = SSOP

Revis ion Designator (will not correlate with datasheet revision)

Device Type

Prefix
ICS = Standard Device

Example:

ICS XXXXXX y F - T

MIN

MAX

MIN

MAX

2.41

2.80

.095

.110

0.20

0.40

.008

.016

0.20

0.34

.008

.0135

0.13

0.25

.005

.010

D
E

10.03

10.68

.395

.420

7.40

7.60

.291

.299

e
h

0.38

0.64

.015

.025

0.50

1.02

.020

.040

0°

8°

0°

8°

VARIATIONS

MIN

MAX

MIN

MAX

18.31

18.55

.720

.730

10-0034

0.635 BASIC

0.025 BASIC

COMMON DIMENSIONS

In Millimeters

In Inches

COMMON DIMENSIONS

Reference Doc.: JEDEC Publication 95, MO-118

300 mil SSOP

SEE VARIATIONS

D mm.

D (inch)

SYMBOL

SEE VARIATIONS

INDEX
AREA

1 2

h x 45°

SEATING
PLANE

- C -

.10 (.004) C

Integrated
Circuit
Systems, Inc.

ICS952623

Advance Information

0758--02/08/05

Ordering Information

ICS952623yGT

Designation for tape and reel packaging

Package Type
G = TSSOP

Revis ion Designator (will not correlate with datasheet revision)

Device Type

Prefix
ICS = Standard Device

Example:

ICS XXXXXX y G - T

INDEX

AREA

INDEX

AREA

1 2

SEATING

PLANE

SEATING

PLANE

- C -

aaa

MIN

MAX

MIN

MAX

1.20

.047

0.05

0.15

.002

.006

0.80

1.05

.032

.041

0.17

0.27

.007

.011

0.09

0.20

.0035

.008

D
E

6.00

6.20

.236

.244

e
L

0.45

0.75

.018

.030

0°

8°

0°

8°

aaa

0.10

.004

VARIATIONS

MIN

MAX

MIN

MAX

13.90

14.10

.547

.555

10-0039

D mm.

D (inch)

Reference Doc.: JEDEC Publication 95, M O-153

0.50 BASIC

0.020 BASIC

SEE VARIATIONS

8.10 BASIC

0.319 BASIC

56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP

(240 mil) (20 mil)

SYMBOL

In Millimeters

In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

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