IS61C512
Integrated Circuit Solution Inc.
1
SR011-0B
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Pin compatible with 128K x 8 devices
High-speed access time: 15, 20, 25, 35 ns
Low active power: 500 mW (typical)
Low standby power
-- 250 W (typical) CMOS standby
Output Enable (
OE) and two Chip Enable
(
CE1 and CE2) inputs for ease in applications
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V (10%) power supply
DESCRIPTION
The
ICSI
IS61C512 is a very high-speed, low power, 65,536
word by 8-bit CMOS static RAMs. They are fabricated using
ICSI
's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields higher performance and low power con-
sumption devices.
When
CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 1 mW (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C512 is available in 32-pin 300mil DIP, SOJ and
8*20mm TSOP-1 packages.
IS61C512
64K x 8 HIGH-SPEED CMOS STATIC RAM
A0-A15
CE1
OE
WE
512 X 1024
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
FUNCTIONAL BLOCK DIAGRAM
IS61C512
2
Integrated Circuit Solution Inc.
SR011-0B
PIN CONFIGURATION
32-Pin DIP and SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A15
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE1
CE1
CE1
CE1
CE1
CE2
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
X
X
L
X
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
H
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
H
X
D
IN
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
10 to +85
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.5
W
I
OUT
DC Output Current (LOW)
20
mA
Notes:
1.
Stress greater than those listed
u n d e r A B S O L U T E M A X I M U M
RATINGS may cause permanent
damage to the device. This is a
stress rating only and functional
operation of the device at these or
any other conditions above those
indicated in the operational sec-
tions of this specification is not
implied. Exposure to absolute
maximum rating conditions for ex-
tended periods may affect reliabil-
ity.
PIN CONFIGURATION
32-Pin TSOP-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
IS61C512
Integrated Circuit Solution Inc.
3
SR011-0B
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
2
2
A
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
2
2
A
Notes:
1.
V
IL
= 3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-15 ns
-20 ns
-25 ns
-35 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
1
Vcc Operating
V
CC
= Max.,
Com.
--
70
--
70
--
70
--
70
mA
Supply Current
I
OUT
= 0 mA, f = 0
Ind.
--
--
--
90
--
90
--
90
I
CC
2
Vcc Dynamic Operating
V
CC
= Max.,
Com.
--
125
--
115
--
105
--
90
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
--
--
135
--
125
--
115
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
--
25
--
25
--
25
--
25
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
--
--
30
--
30
--
30
CE1
V
IH
or
CE2
V
IL
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
750
--
750
--
750
--
750
A
Current (CMOS Inputs)
CE1
V
CC
0.2V,
Ind.
--
--
--
1
--
1
--
1
mA
CE2
0.2V,
V
IN
V
CC
0.2V, or
V
IN
0.2V, f = 0
Notes:
1.
At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
pF
Notes:
1.
Tested initially and after any design or process changes that may affect these parameters.
2.
Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 5.0V.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
5V 10%
Industrial
40C to +85C
5V 10%
IS61C512
4
Integrated Circuit Solution Inc.
SR011-0B
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-15 ns
-20 ns
-25 ns
-35 ns
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
15
--
20
--
25
--
35
--
ns
t
AA
Address Access Time
--
15
--
20
--
25
--
35
ns
t
OHA
Output Hold Time
3
--
3
--
3
--
3
--
ns
t
ACE
1
CE1 Access Time
--
15
--
20
--
25
--
35
ns
t
ACE
2
CE2 Access Time
--
15
--
20
--
25
--
35
ns
t
DOE
OE Access Time
--
7
--
8
--
9
--
12
ns
t
LZOE
(2)
OE to Low-Z Output
0
--
0
--
0
--
0
--
ns
t
HZOE
(2)
OE to High-Z Output
0
6
0
9
0
10
0
12
ns
t
LZCE
1
(2)
CE1 to Low-Z Output
2
--
3
--
3
--
3
--
ns
t
LZCE
2
(2)
CE2 to Low-Z Output
2
--
3
--
3
--
3
--
ns
t
HZCE
(2)
CE1 or CE2 to High-Z Output
0
8
0
9
0
10
0
12
ns
t
PU
(3)
CE1 or CE2 to Power-Up
0
--
0
--
0
--
0
--
ns
t
PD
(3)
CE1 or CE2 to Power-Down
--
12
--
18
--
20
--
20
ns
Notes:
1.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2.
Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3.
Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1a and 1b
AC TEST LOADS
Figure 1a.
Figure 1b.
1213
5 pF
Including
jig and
scope
1378
OUTPUT
3.3V
1213
100 pF
Including
jig and
scope
1378
OUTPUT
3.3V
IS61C512
Integrated Circuit Solution Inc.
5
SR011-0B
DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
50%
50%
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
t
PD
HIGH-Z
t
PU
DATA VALID
t
HZCE
ISB
ADDRESS
OE
CE1
CE2
D
OUT
SUPPLY
CURRENT
ICC
HIGH-Z
Notes:
1.
WE is HIGH for a Read Cycle.
2.
The device is continuously selected.
OE, CE1 = V
IL
, CE2 = V
IH
.
3.
Address is valid prior to or coincident with
CE1 LOW and CE2 HIGH transitions.
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
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