Integrated Circuit Solution Inc.
1
SR025_0C
IS62LV2568L
IS62LV2568LL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The
1+51
IS62LV2568L and IS62LV2568LL are low power
and low V
CC
, 262,144-bit words by 8 bits CMOS static RAMs.
They are fabricated using
1+51
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance and
low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV2568L and IS62LV2568LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
CE2
OE
WE
2048 x 128 x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE1
IS62LV2568L
IS62LV2568LL
256K x 8
LOW POWER and LOW V
++
CMOS STATIC RAM
FEATURES
Access times of 55, 70, 100 ns
Low active power: 126 mW (max, L, LL)
Low standby power: 36 W (max, L) and 7.2
W (max, LL) CMOS standby
Low data retention voltage: 1.5V (min.)
Available in Low Power (-L) and Ultra-Low
Power (-LL)
Output Enable (OE) and two Chip Enable
TTL compatible inputs and outputs
Single 2.7V-3.6V power supply
Available in the 32-pin 8x20mm TSOP-1, 32-pin
8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA
2
Integrated Circuit Solution Inc.
SR025_0C
IS62LV2568L
IS62LV2568LL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN CONFIGURATIONS
32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1
PIN DESCRIPTIONS
A0-A17
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Data Input/Output
NC
No Connection
Vcc
Power
GND
Ground
48-Pin 6*8mm TF-BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
A1
CE2
A3
A6
A8
I/O
4
A2
WE
A4
A7
I/O
0
I/O
5
NC
A5
I/O
1
GND
Vcc
Vcc
GND
I/O
6
NC
A17
I/O
2
I/O
7
OE
CE1
A16
A15
I/O
3
A9
A10
A11
A12
A13
A14
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
2.7V - 3.6V
Industrial
40C to +85C
2.7V - 3.6V
Integrated Circuit Solution Inc.
3
SR025_0C
IS62LV2568L
IS62LV2568LL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.5
V
V
CC
Vcc related to GND
0.3 to +4.0
V
T
BIAS
Temperature Under Bias
40 to +85
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
0.7
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1.0 mA
2.2
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
(1)
Input LOW Voltage
(1)
0.3
0.4
V
I
LI
Input Leakage
GND V
IN
V
CC
1
1
A
I
LO
Output Leakage
GND V
OUT
V
CC
1
1
A
Notes:
1. V
IL
= 2.0V for pulse width less than 10 ns.
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE1
CE1
CE1
CE1
CE1
CE2
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
X
High-Z
I
SB
, I
SB
(Power-down)
X
X
L
X
High-Z
I
SB
, I
SB
Output Disabled
H
L
H
H
High-Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
4
Integrated Circuit Solution Inc.
SR025_0C
IS62LV2568L
IS62LV2568LL
IS62LV2568L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating V
CC
= Max.,
Com.
40
30
20
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
45
35
25
I
SB
TTL Standby Current
V
CC
= Max.,
Com.
0.4
0.4
0.4
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
,
Ind.
1.0
1.0
1.0
CE1 V
IH
or CE2 V
IL
, f = 0
I
SB
CMOS Standby
V
CC
= Max., f = 0
Com.
35
35
35
A
Current (CMOS Inputs)
CE1 V
CC
0.2V,
Ind.
50
50
50
CE2 0.2V,
or V
IN
V
CC
0.2V, V
IN
0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV2568LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating V
CC
= Max.,
Com.
40
30
20
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
45
35
25
I
SB
TTL Standby Current
V
CC
= Max.,
Com.
0.4
0.4
0.4
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
,
Ind.
1.0
1.0
1.0
CE1 V
IH
or CE2 V
IL
, f = 0
I
SB
CMOS Standby
V
CC
= Max., f = 0
Com.
10
10
10
A
Current (CMOS Inputs)
CE V
CC
0.2V,
Ind.
15
15
15
CE2 0.2V,
or V
IN
V
CC
0.2V, V
IN
0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
5
SR025_0C
IS62LV2568L
IS62LV2568LL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-55
-70
-100
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
t
RC
Read Cycle Time
55
70
100
ns
t
AA
Address Access Time
55
70
100
ns
t
OHA
Output Hold Time
10
10
15
ns
t
ACE
1
CE1 Access Time
55
70
100
ns
t
ACE
2
CE2 Access Time
55
70
100
ns
t
DOE
OE Access Time
30
35
50
ns
t
LZOE
(2)
OE to Low-Z Output
5
5
5
ns
t
HZOE
(2)
OE to High-Z Output
20
0
25
0
30
ns
t
LZCE
1
(2)
CE1 to Low-Z Output
10
10
10
ns
t
LZCE
2
(2)
CE2 to Low-Z Output
10
10
10
ns
t
HZCE
(2)
CE1 or CE2 to Low-Z Output
0
20
0
25
0
30
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Times
5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
5 pF
Including
jig and
scope
OUTPUT
1 TTL
100 pF
Including
jig and
scope
OUTPUT
1 TTL
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