Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V Core DC Characteristics
- Power Supply 2.5V Core DC Characteristics
- LVCMOS DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- 2.5V AC Characteristics
- 2.5V/1.8V AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information Diagrams
- Parameter Measurement Information Diagrams continued
- Recommendations for Unused Input and Output Pins
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
2
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
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Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
3
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 3.3V5%, 2.5V5%
OR
1.8V5%,T
A
= -40C
TO
85C
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V5%, V
DDO
= 2.5V5%
OR
1.8V5%, T
A
= -40C
TO
85C
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A
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
4
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V 5%, T
A
= -40C
TO
85C
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40C
TO
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Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
5
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
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HARACTERISTICS
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Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
6
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
5D. AC C
HARACTERISTICS
,
V
DD
= V
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A
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TO
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T
ABLE
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HARACTERISTICS
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DD
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N
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
7
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter (Random)
at 155.52MHz (12kHz - 20MHz)
= 0.18ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
8
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.45%
V
DDO
-0.9V5%
V
DD
0.9V5%
SCOPE
Qx
LVCMOS
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDO
-1.25V5%
V
DD
1.25V5%
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5 C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ART
-
TO
-P
ART
S
KEW
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
SCOPE
Qx
LVCMOS
1.6V5%
V
DDO
-0.9V5%
V
DD
0.9V5%
V
DD
,
V
DDO
GND
V
DD
,
V
DDO
GND
GND
GND
GND
t
sk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
Part 1
Part 2
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
9
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q
tp
LH
V
DDO
2
V
DD
2
CLK0, CLK1
Q
I
NPUT
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PD1
t
PD2
tsk(i) =
t
PD1
t
PD1
CLKx
Q
CLKy
Q
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
10
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83052I is: 967
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
I
NPUTS
:
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
A
PPLICATION
I
NFORMATION
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
11
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
7. P
ACKAGE
D
IMENSIONS
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
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m
u
m
i
n
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m
u
m
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x
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M
N
8
A
-
-
0
2
.
1
1
A
5
0
.
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5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Integrated
Circuit
Systems, Inc.
83052AGI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
12
ICS83052I
2:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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WWW.ALLDATASHEET.COM
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