Электронный компонент: 1893AGILF

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Chapter 1 Abbreviations and Acronyms
Table 1-1. Abbreviations and Acronyms
Chapter 2 Conventions and Nomenclature
Table 2-1. Conventions and Nomenclature
Chapter 3 Typical ICS1893AG Applications
3.1 Typical ICS1893AG Applications
3.2 ICS1893AG Features
Chapter 4 Overview of the ICS1893AG
4.1 100Base-TX Operation
4.2 10Base-T Operation
Chapter 5 Operating Modes Overview
5.1 Reset Operations
5.1.1 General Reset Operations
5.1.1.1 Entering Reset
5.1.1.2 Exiting Reset
5.1.1.3 Hot Insertion
5.1.2 Specific Reset Operations
5.1.2.1 Hardware Reset
5.1.2.2 Power-On Reset
5.1.2.3 Software Reset
5.2 Power-Down Operations
5.3 Automatic Power-Saving Operations
Table 5-1. Automatic Power-Saving Features, 10Base-T and 100Base-TX Modes
5.4 Auto-Negotiation Operations
5.5 100Base-TX Operations
5.6 10Base-T Operations
5.7 Half-Duplex and Full-Duplex Operations
Chapter 6 Interface Overviews
6.1 MII Data Interface
6.2 Serial Management Interface
6.3 Twisted-Pair Interface
6.3.1 Twisted-Pair Transmitter Interface
Figure 6-1. ICS1893AG Transmit Twisted Pair
6.3.2 Twisted-Pair Receiver Interface
Figure 6-2. ICS1893AG Receiver Twisted Pair
6.4 Clock Reference Interface
Figure 6-3. Crystal or Oscillator Operation
Table 6-1. 25MHz Crystal Specification
Table 6-2. 25MHz Oscillator Specification
6.5 Status Interface
Table 6-3. Pins for Monitoring the Data Link
Figure 6-4. ICS1893AG LED - PHY Interface
Chapter 7 Functional Blocks
7.1 Functional Block: Media Independent Interface
7.2 Functional Block: Auto-Negotiation
7.2.1 Auto-Negotiation General Process
Table 7-1. Example of Selection Process of Highest-Priority Technology
7.2.2 Auto-Negotiation: Parallel Detection
7.2.3 Auto-Negotiation: Remote Fault Signaling
7.2.4 Auto-Negotiation: Reset and Restart
7.2.4.1 Auto-Negotiation Reset
7.2.4.2 Auto-Negotiation Restart
7.2.5 Auto-Negotiation: Progress Monitor
7.3 Functional Block: 100Base-X PCS and PMA Sublayers
7.3.1 PCS Sublayer
7.3.2 PMA Sublayer
7.3.3 PCS/PMA Transmit Modules
7.3.3.1 PCS Transmit Module
7.3.3.2 PMA Transmit Module
7.3.4 PCS/PMA Receive Modules
7.3.4.1 PCS Receive Module
7.3.4.2 PMA Receive Modules
7.3.5 PCS Control Signal Generation
7.3.6 4B/5B Encoding/Decoding
7.4 Functional Block: 100Base-TX TP-PMD Operations
7.4.1 100Base-TX Operation: Stream Cipher Scrambler/Descrambler
7.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder
7.4.3 100Base-TX Operation: DC Restoration
7.4.4 100Base-TX Operation: Adaptive Equalizer
7.4.5 100Base-TX Operation: Twisted-Pair Transmitter
7.4.6 100Base-TX Operation: Twisted-Pair Receiver
7.4.7 100Base-TX Operation: Auto Polarity Correction
7.4.8 100Base-TX Operation: Isolation Transformer
7.5 Functional Block: 10Base-T Operations
7.5.1 10Base-T Operation: Manchester Encoder/Decoder
7.5.2 10Base-T Operation: Clock Synthesis
7.5.3 10Base-T Operation: Clock Recovery
7.5.4 10Base-T Operation: Idle
7.5.5 10Base-T Operation: Link Monitor
7.5.6 10Base-T Operation: Smart Squelch
7.5.7 10Base-T Operation: Carrier Detection
7.5.8 10Base-T Operation: Collision Detection
7.5.9 10Base-T Operation: Jabber
7.5.10 10Base-T Operation: SQE Test
7.5.11 10Base-T Operation: Twisted-Pair Transmitter
7.5.12 10Base-T Operation: Twisted-Pair Receiver
7.5.13 10Base-T Operation: Auto Polarity Correction
7.5.14 10Base-T Operation: Isolation Transformer
7.6 Functional Block: Management Interface
7.6.1 Management Register Set Summary
7.6.2 Management Frame Structure
Table 7-2. Management Frame Structure Summary
7.6.2.1 Management Frame Preamble
7.6.2.2 Management Frame Start
7.6.2.3 Management Frame Operation Code
7.6.2.4 Management Frame PHY Address
7.6.2.5 Management Frame Register Address
7.6.2.6 Management Frame Operational Code
7.6.2.7 Management Frame Turnaround
7.6.2.8 Management Frame Data
7.6.2.9 Serial Management Interface Idle State
Chapter 8 Management Register Set
8.1 Introduction to Management Register Set
8.1.1 Management Register Set Outline
Table 8-1. ISO/IEC-Specified Management Register Set
Table 8-2. ICS-Specific Registers
8.1.2 Management Register Bit Access
Table 8-3. Description of Management Register Bit Types
8.1.3 Management Register Bit Default Values
Table 8-4. Range of Possible Valid Default Values for ICS1893AG Register Bits
8.1.4 Management Register Bit Special Functions
8.1.4.1 Latching High Bits
8.1.4.2 Latching Low Bits
8.1.4.3 Latching Maximum Bits
8.1.4.4 Self-Clearing Bits
8.2 Register 0: Control Register
Table 8-5. Control Register (Register 0 [0x00]
8.2.1 Reset (bit 0.15)
8.2.2 Loopback Enable (bit 0.14)
8.2.3 Data Rate Select (bit 0.13)
8.2.4 Auto-Negotiation Enable (bit 0.12)
8.2.5 Low Power Mode (bit 0.11)
8.2.6 Isolate (bit 0.10)
8.2.7 Restart Auto-Negotiation (bit 0.9)
8.2.8 Duplex Mode (bit 0.8)
8.2.9 Collision Test (bit 0.7)
8.2.10 IEEE Reserved Bits (bits 0.6:0)
8.3 Register 1: Status Register
Table 8-6. Status Register (Register 1 [0x01])
8.3.1 100Base-T4 (bit 1.15)
8.3.2 100Base-TX Full Duplex (bit 1.14)
8.3.3 100Base-TX Half Duplex (bit 1.13)
8.3.4 10Base-T Full Duplex (bit 1.12)
8.3.5 10Base-T Half Duplex (bit 1.11)
8.3.6 IEEE Reserved Bits (bits 1.10:7)
8.3.7 MF Preamble Suppression (bit 1.6)
8.3.8 Auto-Negotiation Complete (bit 1.5)
8.3.9 Remote Fault (bit 1.4)
8.3.10 Auto-Negotiation Ability (bit 1.3)
8.3.11 Link Status (bit 1.2)
8.3.12 Jabber Detect (bit 1.1)
8.3.13 Extended Capability (bit 1.0)
8.4 Register 2: PHY Identifier Register
Table 8-7. PHY Identifier Register (Register 2 [0x02])
Table 8-8. IEEE-Assigned Organizationally Unique Identifier
8.5 Register 3: PHY Identifier Register
Table 8-9. PHY Identifier Register (Register 3 [0x03])
8.5.1 OUI bits 19-24 (bits 3.15:10)
8.5.2 Manufacturer's Model Number (bits 3.9:4)
8.5.3 Revision Number (bits 3.3:0)
Table 8-10. ICS1893AG Revision Number
8.6 Register 4: Auto-Negotiation Register
Table 8-11. Auto-Negotiation Advertisement Register (register 4 [0x04])
8.6.1 Next Page (bit 4.15)
8.6.2 IEEE Reserved Bit (bit 4.14)
8.6.3 Remote Fault (bit 4.13)
8.6.4 IEEE Reserved Bits (bits 4.12:10)
8.6.5 Technology Ability Field (bits 4.9:5)
8.6.6 Selector Field (Bits 4.4:0)
8.7 Register 5: Auto-Negotiation Link Partner Ability Register
Table 8-12. Auto-Negotiation Link Partner Ability Register (register 5 [0x05])
8.7.1 Next Page (bit 5.15)
8.7.2 Acknowledge (bit 5.14)
8.7.3 Remote Fault (bit 5.13)
8.7.4 Technology Ability Field (bits 5.12:5)
8.7.5 Selector Field (bits 5.4:0)
8.8 Register 6: Auto-Negotiation Expansion Register
Table 8-13. Auto-Negotiation Expansion Register (register 6 [0x06])
8.8.1 IEEE Reserved Bits (bits 6.15:5)
8.8.2 Parallel Detection Fault (bit 6.4)
8.8.3 Link Partner Next Page Able (bit 6.3)
8.8.4 Next Page Able (bit 6.2)
8.8.5 Page Received (bit 6.1)
8.8.6 Link Partner Auto-Negotiation Able (bit 6.0)
8.9 Register 7: Auto-Negotiation Next Page Transmit Register
Table 8-14. Auto-Negotiation Next Page Transmit Register (register 7 [0x07])
8.9.1 Next Page (bit 7.15)
8.9.2 IEEE Reserved Bit (bit 7.14)
8.9.3 Message Page (bit 7.13)
8.9.4 Acknowledge 2 (bit 7.12)
8.9.5 Toggle (bit 7.11)
8.9.6 Message Code Field / Unformatted Code Field (bits 7.10:0)
8.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register
Table 8-15. Auto-Negotiation Next Page Link Partner Ability Register (register 8 [0x08])
8.10.1 Next Page (bit 8.15)
8.10.2 IEEE Reserved Bit (bit 8.14)
8.10.3 Message Page (bit 8.13)
8.10.4 Acknowledge 2 (bit 8.12)
8.10.5 Message Code Field / Unformatted Code Field (bits 8.10:0)
8.11 Register 16: Extended Control Register
Table 8-16. Extended Control Register (register 16 [0x10])
8.11.1 Command Override Write Enable (bit 16.15)
8.11.2 ICS Reserved (bits 16.14:11)
8.11.3 PHY Address (bits 16.10:6)
8.11.4 Stream Cipher Scrambler Test Mode (bit 16.5)
8.11.5 ICS Reserved (bit 16.4)
8.11.6 NRZ/NRZI Encoding (bit 16.3)
8.11.7 Invalid Error Code Test (bit 16.2)
Table 8-17. Invalid Error Code Translation Table
8.11.8 ICS Reserved (bit 16.1)
8.11.9 Stream Cipher Disable (bit 16.0)
8.12 Register 17: Quick Poll Detailed Status Register
Table 8-18. Quick Poll Detailed Status Register (register 17 [0x11])
8.12.1 Data Rate (bit 17.15)
8.12.2 Duplex (bit 17.14)
8.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11)
Table 8-19. Auto-Negotiation State Machine (Progress Monitor)
8.12.4 100Base-TX Receive Signal Lost (bit 17.10)
8.12.5 100Base PLL Lock Error (bit 17.9)
8.12.6 False Carrier (bit 17.8)
8.12.7 Invalid Symbol (bit 17.7)
8.12.8 Halt Symbol (bit 17.6)
8.12.9 Premature End (bit 17.5)
8.12.10 Auto-Negotiation Complete (bit 17.4)
8.12.11 100Base-TX Signal Detect (bit 17.3)
8.12.12 Jabber Detect (bit 17.2)
8.12.13 Remote Fault (bit 17.1)
8.12.14 Link Status (bit 17.0)
8.13 Register 18: 10Base-T Operations Register
Table 8-20. 10Base-T Operations Register (register 18 [0x12])
8.13.1 Remote Jabber Detect (bit 18.15)
8.13.2 Polarity Reversed (bit 18.14)
8.13.3 ICS Reserved (bits 18.13:6)
8.13.4 Jabber Inhibit (bit 18.5)
8.13.5 ICS Reserved (bit 18.4)
8.13.6 Auto Polarity Inhibit (bit 18.3)
8.13.7 SQE Test Inhibit (bit 18.2)
8.13.8 Link Loss Inhibit (bit 18.1)
8.13.9 Squelch Inhibit (bit 18.0)
8.14 Register 19: Extended Control Register 2
Table 8-21. Extended Control Register (register [0x13])
8.14.1 Node/Repeater Configuration (bit 19.15)
8.14.2 Hardware/Software Priority Status (bit 19.14)
8.14.3 Remote Fault (bit 19.13)
8.14.4 ICS Reserved (bits 19.12:8)
8.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7)
8.14.6 ICS Reserved (bits 19.6:1)
8.14.7 Automatic 100Base-TX Power-Down (bit 19.0)
Chapter 9 Pin Diagram, Listings, and Descriptions
9.1 ICS1893AG Pin Diagram
9.2 ICS1893AG Pin Descriptions
Table 9-1. MAC/Repeater Interface Pins
Table 9-2. Transformer Interface Pins
Table 9-3. Multifunction Pins: PHY Address and LED Pins
Table 9-4. Configuration Pins
9.2.1 Transformer Interface Pins
Table 9-5. Transformer Interface Pins
9.2.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins
Table 9-6. PHY Address and LED Pins
9.2.3 Configuration Pins
Table 9-7. Configuration Pins
9.2.4 MAC Interface Pins
9.2.4.1 MAC Interface Pins for Media Independent Interface
Table 9-8. MAC/Repeater Interface Pins: Media Independent Interface (MII)
9.2.5 Ground and Power Pins
Table 9-9. Ground and Power Pins
Chapter 10 DC and AC Operating Conditions
10.1 Absolute Maximum Ratings
Table 10-1. Absolute Maximum Ratings for ICS1893AG
10.2 Recommended Operating Conditions
Table 10-2. Recommended Operating Conditions for ICS1893AG
10.3 Recommended Component Values
Table 10-3. Recommended Component Values for ICS1893AG
Figure 10-1. ICS1893AG 10TCSR and 100TCSR
10.4 DC Operating Characteristics
10.4.1 DC Operating Characteristics for Supply Current
Table 10-4. DC Operating Characteristics for Supply Current
10.4.2 DC Operating Characteristics for TTL Inputs and Outputs
Table 10-5. 3.3-V DC Operating Characteristics for TTL Inputs and Outputs
10.4.3 DC Operating Characteristics for REF_IN
Table 10-6. 3.3-V DC Operating Characteristics for REF_IN
10.4.4 DC Operating Characteristics for Media Independent Interface
Table 10-7. DC Operating Characteristics for Media Independent Interface
10.5 Timing Diagrams
10.5.1 Timing for Clock Reference In (REF_IN) Pin
Table 10-8. REF_IN Timing
Figure 10-2. REF_IN Timing Diagram
10.5.2 Timing for Transmit Clock (TXCLK) Pins
Table 10-9. Transmit Clock Timing
Figure 10-3. Transmit Clock Timing Diagram
10.5.3 Timing for Receive Clock (RXCLK) Pins
Table 10-10. MII Receive Clock Timing
Figure 10-4. Receive Clock Timing Diagram
10.5.4 100M MII: Synchronous Transmit Timing
Table 10-11. 100M MII / 100M Stream Interface: Synchronous Transmit Timing
Figure 10-5. 100M MII / 100M Stream Interface Synchronous Transmit Timing Diagram
10.5.5 10M MII: Synchronous Transmit Timing
Table 10-12. 10M MII: Synchronous Transmit Timing
Figure 10-6. 10M MII Synchronous Transmit Timing Diagram
10.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing
Table 10-13. MII Interface: Synchronous Receive Timing
Figure 10-7. MII Interface Synchronous Receive Timing Diagram
10.5.7 MII Management Interface Timing
Table 10-14. MII Management Interface Timing
Figure 10-8. MII Management Interface Timing Diagram
10.5.8 10M Media Independent Interface: Receive Latency
Table 10-15. 10M MII Receive Latency
Figure 10-9. 10M MII Receive Latency Timing Diagram
10.5.9 10M Media Independent Interface: Transmit Latency
Table 10-16. 10M MII Transmit Latency Timing
Figure 10-10. 10M MII Transmit Latency Timing Diagram
10.5.10 100M / MII Media Independent Interface: Transmit Latency
Table 10-17. MII / 100M Stream Interface Transmit Latency
Figure 10-11. MII / 100M Stream Interface Transmit Latency Timing Diagram
10.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 10-18. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Figure 10-12. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
10.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 10-19. 10M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Figure 10-13. 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
10.5.13 100M MII Media Independent Interface: Receive Latency
Table 10-20. 100M MII / 100M Stream Interface Receive Latency Timing
Figure 10-14. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram
10.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-21. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing
Figure 10-15. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
10.5.15 Reset: Power-On Reset
Table 10-22. Power-On Reset Timing
Figure 10-16. Power-On Reset Timing Diagram
10.5.16 Reset: Hardware Reset and Power-Down
Table 10-23. Hardware Reset and Power-Down Timing
Figure 10-17. Hardware Reset and Power-Down Timing Diagram
10.5.17 10Base-T: Heartbeat Timing (SQE)
Table 10-24. 10Base-T Heartbeat (SQE) Timing
Figure 10-18. 10Base-T Heartbeat (SQE) Timing Diagram
10.5.18 10Base-T: Jabber Timing
Table 10-25. 10Base-T Jabber Timing
Figure 10-19. 10Base-T Jabber Timing Diagram
10.5.19 10Base-T: Normal Link Pulse Timing
Table 10-26. 10Base-T Normal Link Pulse Timing
Figure 10-20. 10Base-T Normal Link Pulse Timing Diagram
10.5.20 Auto-Negotiation Fast Link Pulse Timing
Table 10-27. Auto-Negotiation Fast Link Pulse Timing
Figure 10-21. Auto-Negotiation Fast Link Pulse Timing Diagram
Chapter 11 Physical Dimensions of ICS1893AG Package
Figure 11-1. ICS1893AG Physical Dimensions (56-pin TSSOP, 240 mil Body, 0.50 mm pitch)
Chapter 12 Ordering Information
Figure 12-1. shows ordering information for the ICS1893AG.

ICS1893AG, Rev. A 04/14/05

April, 2005

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

Integrated Circuit Systems, Inc.

3.3 V 10Base-T/100Base-TX Integrated PHYceiver

ICS1893AG

Document Type:

Data Sheet

Document Stage: Preliminary

Features
�

Single 3.3 V �10% power supply

�

Supports category 5 cables with attenuation in excess of

24dB at 100 MHz across a temperature range from 0�C to

+70�C. Industrial temperature version is also available.

�

DSP-based baseline wander correction to virtually

eliminate killer packets

�

Low-power, 0.35-micron CMOS (typically 400 mW)

�

Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

�

10Base-T and 100Base-TX IEEE 802.3 compliant

�

Clock or crystal supported

�

Media Independent Interface (MII) supported

�

Managed or Unmanaged Applications

�

10M or 100M Half and Full Duplex Modes

�

Auto-Negotiation with Next Page. Parallel detection for

Legacy products

�

Fully integrated, DSP-based PMD includes:

� Adaptive equalization and baseline wander correction
� Transmit wave shaping and stream cipher scrambler
� MLT-3 encoder and NRZ/NRZI encoder

�

Loopback mode for Diagnostic Functions

�

Small footprint 56-pin 240 mil TSSOP package.

General

The ICS1893AG is a re-packaged version of the ICS1893AF
in a 56-lead TSSOP 240 mil package. The ICS1893AG is a
fully integrated, Physical Layer device (PHY) that is
compliant with both the 10Base-T and 100Base-TX
CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The
ICS1893AG uses the same proven silicon as the
ICS1893AF but offers a smaller form factor solution to users
where physical package size is important.

All parametric specification and timing diagrams for the
ICS1893AF apply to the ICS1893AG. Refer to the
ICS1893AF datasheet for detailed specifications and timing.

The ICS1893AG uses the same twisted-pair transmit and
receive circuits as the ICS1893AF, and the same
recommended board layout techniques apply to the
ICS1893AG.

The ICS1893AG is intended for Node applications using the
standard MII interface to the MAC.

Clock

Power

LEDs and PHY
Address

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

Integrated

Switch

MII

Extended

Register

Set

Interface

MUX

ICS1893AG Block Diagram

PCS

�

Framer

�

CRS/COL
Detection

�

Parallel to Serial

�

4B/5B

Auto-

Negotiation

10Base-T

100Base-TX

TP_PMD

�

MLT-3

�

Stream Cipher

�

Adaptive Equalizer

�

Baseline Wander
Correction

PMA

�

Clock Recovery

�

Link Monitor

�

Signal Detection

�

Error Detection

Low-Jitter

Clock

Synthesizer

Configuration

and Status

10/100 MII

MAC

Interface

MII

Management

Interface

ICS1893AG, Rev A 04/14/05

April, 2005

Table of Contents

ICS1893AG Data Sheet - Preliminary

Table of Contents

Section

Title

Page

Revision History

............................................................................................................................. 9

Chapter 1

Abbreviations and Acronyms ......................................................................................... 10

Chapter 2

Conventions and Nomenclature..................................................................................... 12

Chapter 3

Typical ICS1893AG Applications .................................................................................... 14

3.1

ICS1893AG / ICS1893AF Pin Differences..............................................................14

3.2

ICS1893AG / ICS1893AF Shared Features ...........................................................15

Chapter 4

Overview of the ICS1893AG ............................................................................................ 16

4.1 100Base-TX

Operation

..........................................................................................17

4.2 10Base-T

Operation

...............................................................................................17

Chapter 5

Operating Modes Overview............................................................................................. 18

5.1 Reset

Operations

...................................................................................................19

5.1.1 General

Reset

Operations

.....................................................................................19

5.1.2 Specific

Reset

Operations

.....................................................................................20

5.2 Power-Down

Operations

........................................................................................21

5.3 Automatic

Power-Saving

Operations

.....................................................................22

5.4 Auto-Negotiation

Operations

..................................................................................22

5.5 100Base-TX

Operations

........................................................................................23

5.6 10Base-T

Operations

.............................................................................................23

5.7

Half-Duplex and Full-Duplex Operations ...............................................................23

Chapter 6

Interface Overviews.......................................................................................................... 24

6.1

MII Data Interface ..................................................................................................25

6.2

Serial Management Interface .................................................................................26

6.3 Twisted-Pair

Interface

............................................................................................26

6.3.1 Twisted-Pair

Transmitter

Interface

.........................................................................27

6.3.2 Twisted-Pair

Receiver Interface .............................................................................28

6.4 Clock

Reference

Interface

.....................................................................................29

6.5 Status

Interface

......................................................................................................31

Chapter 7

Functional Blocks............................................................................................................. 33

7.1

Functional Block: Media Independent Interface .....................................................34

7.2

Functional Block: Auto-Negotiation ........................................................................35

7.2.1 Auto-Negotiation

General

Process

........................................................................36

7.2.2 Auto-Negotiation:

Parallel Detection ......................................................................37

7.2.3

Auto-Negotiation: Remote Fault Signaling .............................................................37

7.2.4 Auto-Negotiation:

Reset

and Restart .....................................................................38

7.2.5 Auto-Negotiation:

Progress Monitor .......................................................................38

Table of Contents

ICS1893AG, Rev. A 04/14/05

April, 2005

ICS1893AG Data Sheet - Preliminary

Table of Contents

Section

Title

Page

7.3

Functional Block: 100Base-X PCS and PMA Sublayers ........................................40

7.3.1 PCS

Sublayer

........................................................................................................40

7.3.2 PMA

Sublayer

........................................................................................................40

7.3.3

PCS/PMA Transmit Modules .................................................................................41

7.3.4

PCS/PMA Receive Modules ..................................................................................42

7.3.5

PCS Control Signal Generation .............................................................................43

7.3.6 4B/5B

Encoding/Decoding

.....................................................................................43

7.4

Functional Block: 100Base-TX TP-PMD Operations .............................................44

7.4.1 100Base-TX

Operation:

Stream Cipher Scrambler/Descrambler ..........................44

7.4.2

100Base-TX Operation: MLT-3 Encoder/Decoder .................................................44

7.4.3

100Base-TX Operation: DC Restoration ................................................................44

7.4.4

100Base-TX Operation: Adaptive Equalizer ..........................................................45

7.4.5

100Base-TX Operation: Twisted-Pair Transmitter .................................................45

7.4.6

100Base-TX Operation: Twisted-Pair Receiver .....................................................45

7.4.7

100Base-TX Operation: Auto Polarity Correction ..................................................46

7.4.8

100Base-TX Operation: Isolation Transformer ......................................................46

7.5

Functional Block: 10Base-T Operations ................................................................47

7.5.1

10Base-T Operation: Manchester Encoder/Decoder .............................................47

7.5.2

10Base-T Operation: Clock Synthesis ...................................................................47

7.5.3

10Base-T Operation: Clock Recovery ...................................................................47

7.5.4

10Base-T Operation: Idle .......................................................................................48

7.5.5

10Base-T Operation: Link Monitor .........................................................................48

7.5.6

10Base-T Operation: Smart Squelch .....................................................................49

7.5.7

10Base-T Operation: Carrier Detection .................................................................49

7.5.8

10Base-T Operation: Collision Detection ...............................................................49

7.5.9

10Base-T Operation: Jabber ..................................................................................50

7.5.10 10Base-T

Operation: SQE Test .............................................................................50

7.5.11 10Base-T

Operation: Twisted-Pair Transmitter .....................................................51

7.5.12 10Base-T

Operation: Twisted-Pair Receiver .........................................................51

7.5.13 10Base-T

Operation: Auto Polarity Correction .......................................................51

7.5.14 10Base-T

Operation: Isolation Transformer ...........................................................51

7.6

Functional Block: Management Interface ...............................................................52

7.6.1

Management Register Set Summary .....................................................................52

7.6.2

Management Frame Structure ...............................................................................52

ICS1893AG, Rev A 04/14/05

April, 2005

Table of Contents

ICS1893AG Data Sheet - Preliminary

Table of Contents

Section

Title

Page

Chapter 8

Management Register Set ............................................................................................... 55

8.1

Introduction to Management Register Set .............................................................56

8.1.1

Management Register Set Outline .........................................................................56

8.1.2

Management Register Bit Access ..........................................................................57

8.1.3

Management Register Bit Default Values ..............................................................57

8.1.4

Management Register Bit Special Functions .........................................................58

8.2

8.2.1

Reset (bit 0.15) ......................................................................................................59

8.2.2

Loopback Enable (bit 0.14) ....................................................................................60

8.2.3

Data Rate Select (bit 0.13) .....................................................................................60

8.2.4

Auto-Negotiation Enable (bit 0.12) .........................................................................60

8.2.5

Low Power Mode (bit 0.11) ....................................................................................61

8.2.6 Isolate

(bit

0.10)

.....................................................................................................61

8.2.7

Restart Auto-Negotiation (bit 0.9) ..........................................................................61

8.2.8

Duplex Mode (bit 0.8) .............................................................................................62

8.2.9

Collision Test (bit 0.7) ............................................................................................62

8.2.10

IEEE Reserved Bits (bits 0.6:0) .............................................................................62

8.3

8.3.1 100Base-T4

(bit

1.15)

............................................................................................63

8.3.2

100Base-TX Full Duplex (bit 1.14) .........................................................................64

8.3.3

100Base-TX Half Duplex (bit 1.13) ........................................................................64

8.3.4 10Base-T

Full Duplex (bit 1.12) .............................................................................64

8.3.5

10Base-T Half Duplex (bit 1.11) .............................................................................64

8.3.6

IEEE Reserved Bits (bits 1.10:7) ...........................................................................65

8.3.7

MF Preamble Suppression (bit 1.6) .......................................................................65

8.3.8 Auto-Negotiation

Complete (bit 1.5) .......................................................................65

8.3.9

Remote Fault (bit 1.4) ............................................................................................66

8.3.10

Auto-Negotiation Ability (bit 1.3) ............................................................................66

8.3.11

Link Status (bit 1.2) ................................................................................................67

8.3.12

Jabber Detect (bit 1.1) ...........................................................................................67

8.3.13

Extended Capability (bit 1.0) ..................................................................................67

8.4

Table of Contents

ICS1893AG, Rev. A 04/14/05

April, 2005

ICS1893AG Data Sheet - Preliminary

Table of Contents

Section

Title

Page

8.5

8.5.1

OUI bits 19-24 (bits 3.15:10) ..................................................................................70

8.5.2

Manufacturer's Model Number (bits 3.9:4) .............................................................71

8.5.3

Revision Number (bits 3.3:0) .................................................................................71

8.6

8.6.1

Next Page (bit 4.15) ...............................................................................................72

8.6.2

IEEE Reserved Bit (bit 4.14) ..................................................................................72

8.6.3

Remote Fault (bit 4.13) ..........................................................................................73

8.6.4

IEEE Reserved Bits (bits 4.12:10) .........................................................................73

8.6.5

Technology Ability Field (bits 4.9:5) .......................................................................74

8.6.6

Selector Field (Bits 4.4:0) .......................................................................................75

8.7

8.7.1

Next Page (bit 5.15) ...............................................................................................76

8.7.2 Acknowledge

(bit

5.14)

..........................................................................................77

8.7.3

Remote Fault (bit 5.13) ..........................................................................................77

8.7.4

Technology Ability Field (bits 5.12:5) .....................................................................77

8.7.5

Selector Field (bits 5.4:0) .......................................................................................77

8.8

8.8.1

IEEE Reserved Bits (bits 6.15:5) ...........................................................................78

8.8.2

Parallel Detection Fault (bit 6.4) .............................................................................79

8.8.3

Link Partner Next Page Able (bit 6.3) ....................................................................79

8.8.4

Next Page Able (bit 6.2) .........................................................................................79

8.8.5

Page Received (bit 6.1) .........................................................................................79

8.8.6 Link

Partner

Auto-Negotiation Able (bit 6.0) ..........................................................79

8.9

8.9.1

Next Page (bit 7.15) ...............................................................................................81

8.9.2

IEEE Reserved Bit (bit 7.14) ..................................................................................81

8.9.3

Message Page (bit 7.13) ........................................................................................81

8.9.4

Acknowledge 2 (bit 7.12) .......................................................................................81

8.9.5

Toggle (bit 7.11) .....................................................................................................81

8.9.6

Message Code Field / Unformatted Code Field (bits 7.10:0) .................................81

8.10

8.10.1

Next Page (bit 8.15) ...............................................................................................83

8.10.2

IEEE Reserved Bit (bit 8.14) ..................................................................................83

8.10.3

Message Page (bit 8.13) ........................................................................................83

8.10.4

Acknowledge 2 (bit 8.12) .......................................................................................83

8.10.5

Message Code Field / Unformatted Code Field (bits 8.10:0) .................................83