840001AK-31
www.icst.com/products/hiperclocks.html
REV. A MAY 4, 2005
1
Integrated
Circuit
Systems, Inc.
ICS840001-31
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS840001-31 is a two output LVCMOS/
LVTTL Synthesizer and a member of the
HiPerClocks
TM
family of high perfor mance
devices from ICS. One output is the LVCMOS/
LVTTL main synthesized clock output (Q) and one
output is a three-state LVCMOS/LVTTL reference clock
(REF_CLK) output at the frequency of the crystal oscillator.
The device can accept 26.5625MHz and 40MHz crystals and
can synthesize 106.25MHz or 100MHz outputs. The
ICS840001-31 has excellent <1ps phase jitter performance
over the 637kHz 10MHz integration range. The ICS840001-
31 is packaged in a 3mm x 3mm 16-pin VFQFN, making it
ideal for use on space constrained boards.
F
EATURES
(2) LVCMOS/LVTTL outputs, 20 typical output impedence
(1) Main clock output (Q)
(1) Three-state reference clock output (REF_CLK)
Crystal oscillator interface can accept 26.5625MHz or
40MHz 18pF parallel resonant crystals
Output frequency range: 106.25MHz or 100MHz
VCO range: 490MHz to 640MHz
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.38ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
OSC
Phase
Detector
VCO
490MHz - 640MHz
6
1 = 15
(default)
0 = 24
XTAL_IN
XTAL_OUT
OE
Q
M
(Pullup)
ICS840001-31
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
OE
XTAL_IN
XTAL_OUT
M
Q
V
DDO
GND
V
DD
nc
nc
nc
NC
V
DDA
nc
nc
REF_CLK
1
2
3
4
12
11
10
9
5 6 7 8
16 15 14 13
REF_CLK
(Pullup)
F
UNCTION
T
ABLE
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The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840001-31AK
www.icst.com/products/hiperclocks.html
REV. A MAY 4, 2005
2
Integrated
Circuit
Systems, Inc.
ICS840001-31
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
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840001AK-31
www.icst.com/products/hiperclocks.html
REV. A MAY 4, 2005
3
Integrated
Circuit
Systems, Inc.
ICS840001-31
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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5. C
RYSTAL
C
HARACTERISTICS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
51.5C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
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840001-31AK
www.icst.com/products/hiperclocks.html
REV. A MAY 4, 2005
4
Integrated
Circuit
Systems, Inc.
ICS840001-31
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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840001AK-31
www.icst.com/products/hiperclocks.html
REV. A MAY 4, 2005
5
Integrated
Circuit
Systems, Inc.
ICS840001-31
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
t
PW
Q0
GND
V
DD,
V
DDA,
V
DDO
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
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