MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
1
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Packaged in 20 pin SOIC
3.3 V 5% operation
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock,
or 10 to 50 MHz
Locks to 8 kHz 100 ppm (External mode)
Buffer Mode allows jitter attenuation of
10-50 MHz input and x1/x0.5 or x1/x2 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3,
and OC3 submultiples
See the MK2049-01, -02, and -03 for more
selections at VDD = 5 V, and the MK2049-34 for
more selections at 3.3 V
The MK2049-36 is a Phase-Locked Loop (PLL) based
clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference,
the MK2049-36 generates T1, E1, T3, E3, OC3,
Gigabit Ethernet, and other communications
frequencies. This allows for the generation of clocks
frequency-locked to an 8 kHz backplane clock,
simplifying clock synchronization in communications
systems.
This part also has a jitter-attenuated Buffer capability. In
this mode, the MK2049-36 is ideal for filtering jitter
from with high jitter clocks.
ICS can customize these devices for many other
different frequencies. Contact your ICS representative
for more details.
Block Diagram
Description
Features
VDD
GND
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
External/
Buffer Mode
Mux
FS3:0
Clock
Input
CAP1
CAP2
CLK
CLK/2
Output
Buffer
8 kHz
(External
Mode only)
Crystal
Oscillator
Reference
Crystal
X1
X2
4
3
3
RES
FCAP
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
2
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Pin Descriptions
Type:
XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
Pin Assignment
20 pin (300 mil) SOIC
1
16
2
3
4
15
14
13
VDD
GND
X2
VDD
GND
5
6
7
8
12
11
10
9
FS3
X1
FS1
FS0
CAP1
ICLK
8K
CLK/2
CLK
18
17
19
20
FCAP
VDD
FS2
GND
CAP2
RES
Number Name
Type Description
1
FS1
I
Frequency Select 1. Determines CLK input/outputs per tables on page 4.
2
X2
XO
Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
3
X1
XI
Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
4
VDD
P
Connect to +3.3V.
5
FCAP
-
Filter Capacitor. Connect a 1000 pF ceramic capacitor to ground.
6
VDD
P
Connect to +3.3V.
7
GND
P
Connect to ground.
8
CLK
O
Clock output determined by status of FS3:0 per tables on page 4.
9
CLK/2
O
Clock output determined by status of FS3:0 per tables on page 4. Always 1/2 of CLK.
10
8K
O
Recovered 8 kHz clock output.
11
FS2
I
Frequency Select 2. Determines CLK input/outputs per tables on page 4.
12
FS3
I
Frequency Select 3. Determines CLK input/outputs per tables on page 4.
13
ICLK
I
Input clock connection. Connect to 8 kHz backplane or MHz clock.
14
GND
P
Connect to ground.
15
VDD
P
Connect to +3.3V.
16
CAP1
LF
Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
17
GND
P
Connect to ground.
18
CAP2
LF
Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
19
RES
-
Connect a 10-200k
resistor to ground. Contact ICS at 408-297-1201 for recommended value.
20
FS0
I
Frequency Select 0. Determines CLK input/outputs per tables on page 4.
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
3
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
-40
85
C
Soldering Temperature
Max of 10 seconds
250
C
Storage Temperature
-65
150
C
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
3.15
3.3
3.45
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH, CMOS level
IOH=-4 mA
VDD-0.4
V
Output High Voltage, VOH
IOH=-8 mA
2.4
V
Output Low Voltage
IOL=8 mA
0.4
V
Operating Supply Current, IDD
No Load, VDD=3.3V
7
mA
Short Circuit Current
Each output
50
mA
Input Capacitance, FS3:0
5
pF
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Frequency, External Mode
ICLK
8.000
kHz
Input Clock Pulse Width
10
ns
Propagation Delay
ICLK to 8 kHz
7
ns
Delay, CLK/2 after CLK
1
ns
Output Clock Rise Time
0.8 to 2.0 V
2
ns
Output Clock Fall Time
2.0 to 0.8 V
2
ns
Output Clock Duty Cycle, High Time
At VDD/2, except 8k
40
60
%
Actual mean frequency error versus target
Any clock selection
0
0
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device.
Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
Electrical Specifications
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
4
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
0 = connect directly to ground, 1 = connect directly to VDD.
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
MK2049-36 Output Decoding Table External Mode (MHz)
ICLK
F S 3 F S 2 F S 1 F S 0
C L K / 2
CLK
8 K
Crystal
8 kHz
0
0
0
0
1.544
3.088
8 kHz
12.352
8 kHz
0
0
0
1
2.048
4.096
8 kHz
12.288
8 kHz
0
0
1
0
22.368
44.736
8 kHz
11.184
8 kHz
0
0
1
1
17.184
34.368
8 kHz
11.456
8 kHz
0
1
0
0
77.76
155.52
8 kHz
19.44
8 kHz
0
1
0
1
16.384
32.768
8 kHz
16.384
8 kHz
0
1
1
0
14.352
28.704
8 kHz
14.352
8 kHz
0
1
1
1
TEST
TEST
TEST
TEST
8 kHz
1
0
0
0
18.528
37.056
8 kHz
18.528
8 kHz
1
0
0
1
12.352
24.704
8 kHz
24.704
8 kHz
1
0
1
0
7.68
15.36
8 kHz
15.36
8 kHz
1
0
1
1
TEST
TEST
TEST
TEST
8 kHz
1
1
0
0
12.288
24.576
8 kHz
24.576
8 kHz
1
1
0
1
16.384
32.768
8 kHz
12.288
ICLK
F S 3 F S 2 F S 1 F S 0
C L K / 2
CLK
8 K
Crystal
22 - 36
1
1
1
0
ICLK/2
ICLK
N/A
ICLK/2
11 - 18
1
1
1
1
2*ICLK
4*ICLK
N/A
ICLK
MK2049-36 Output Decoding Table Buffer Mode (MHz)
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
5
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
OPERATING MODES
The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock to
generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication clock
frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a "high" or "on" pulse as narrow as 10
ns is acceptable.
Buffer Mode
Unlike the other mode that accepts only a single specified input frequency, Buffer Mode will accept a wider range of
input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also provide the option of getting x1,
x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock,
generating low-jitter 27 MHz and 13.5 MHz outputs.
FREQUENCY LOCKING TO THE INPUT
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary 40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by
up to 60 ppm and still have the output clock remain frequency-locked.
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
6
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Loop Filter Components
CAP2
CAP1
5.6 nF
Crystal Operation
The MK2049 operates by phase locking the input signal to a VCXO which consists of the special recommended
crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and reliability, the
layout guidelines must be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The
MK2049 has variable load capacitors on-chip which "pull", or change the frequency of the crystal. External stray
capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should
use short traces between the MK2049 and the crystal.
For the VCXO to operate correctly, a crystal properly specified and matched to the MK2049-36 must be used. For
more information, including a list of recommended crystals, refer to application note MAN05.
The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 3 below, and as close to
the chip as possible. High quality ceramic capacitors are recommended. DO NOT use any type of polarized or
electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Another alternative is the Panasonic
PPS polymer dielectric series; their part number for the 0.1 F cap is ECHU1C104JB5. Avoid high-K dielectrics like
Z5U and X7R; these and other ceramics which have piezolectric properties allow mechanical vibration in the system
to increase the output jitter because the mechanical energy is converted directly to voltage noise on the VCO input.
The MK2049-36 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01F must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17), and
33
series terminating resistors should be used on clock outputs with traces longer than 1 inch (assuming 50
traces). The selection of additional external components is described in the following sections.
EXTERNAL COMPONENT SELECTION
470 k
0.1 F
Figure 3. Loop Filter Component Values
(Typical component values are shown. Contact the ICS applications department at
(408)297-1201 for the recommended values for your application)
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
7
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Determining the Crystal Frequency Adjustment Capacitors
To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a frequency
counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals
which you plan to use in production, along with measured initial accuracy for each crystal at the specified load
capacitance, CL .
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049 to 3.3 V. Connect pin 18 of the MK2049 to the second power supply. Adjust the
voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK or CLK/2 output .
2. Adjust the voltage on pin 18 to 3.3 V. Measure and record the frequency of the same output.
To calculate the centering error:
Centering error = 106
(f
3.3V
-
f
target
) + (f
0.0V
- f
target
)
f
target
- errorxtal
Where ftarget = 44.736000 MHz, for example, and errorxtal =
actual initial accuracy (in ppm) of the
crystal being measured.
If the centering error is less than 15 ppm, no adjustment is needed. If the centering error is more than 15 ppm
negative, the PC board has too much stray capacitance and will need to be redone with a new layout to reduce stray
capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS for details.) If the
centering error is more than 15 ppm positive, add identical fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor = 2*(centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is
30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (less than
15 ppm).
The ICS applications department can perform this procedure on your board. Call us at 4082959800, and we will
arrange for you to send us a PC board (stuffed or unstuffed) and one of your crystals. We will calculate the value of
capacitors needed.
EXTERNAL COMPONENT SELECTION (continued)
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
8
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
PC BOARD LAYOUT
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins are very
sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two
capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15
and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output
clocks on pins 8 and 9 should have a series termination of 33
connected close to the pin. Additional improvements
will come from keeping all components on the same side of the board, minimizing vias through other signal layers, and
routing other signals away from the MK2049. You may also refer to MAN05 for additional suggestions on layout of the
crystal section.
The crystal traces should include pads for small capacitors from X1 and X2 to ground; these are used to adjust the
stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is
accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not
adjusted with these fixed capacitors. However, ICS MicroClock recommends that the adjustment capacitors be
included to minimize the effects of variation in individual crystals, temperature, and aging. The value of these
capacitors (typically 0-4 pF) is determined once for a given board layout, using the procedure described in the section
titled "Determining the Crystal Frequency Adjustment Capacitors".
=connect to VDD
=connect to GND
V
G
1
16
2
3
15
14
13
8
12
11
10
9
18
20
cap
resist.
cap
G
V
19
17
V
resist.
resist.
cap
Figure 2. Typical MK2049-36 Layout
7
cap
cap
G
Optional;
see text
Cutout in ground and power plane.
Route all traces away from this area.
5
resist.
G
cap
6
4
cap
MK2049-36
3.3 V Communications Clock PLL
MDS 2049-36 B
9
Revision 091801
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Ordering Information
Part/Order Number
Marking
Package
Temperature
MK2049-36SI
MK2049-36SI
20 pin SOIC
-40 to 85 C
MK2049-36SITR
MK2049-36SI
Add Tape & Reel
-40 to 85 C
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
20 pin SOIC
Inches
Inches
Millimeters
Millimeters
Symbol
Min
Max
Min
Max
A
--
0.104
--
2.65
A1
0.0040
--
0.10
--
B
0.013
0.020
0.33
0.51
C
0.007
0.013
0.18
0.33
D
0.496
0.512
12.60
13.00
E
0.291
0.299
7.40
7.60
e .050 BSC
.050 BSC
1.27 BSC
1.27 BSC
H
0.394
0.419
10.01
10.64
h
0.01
0.029
0.25
0.74
L
0.016
0.050
0.41
1.27
B
D
E
H
e
A1
C
A
h x 45
L
INDEX
AREA
1
2
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