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Электронный компонент: 2069-01

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MK2069-01
MDS 2069-01 G
1
Revision 020503
I n t e g r a t e d Ci r c u i t S y s t e m s
q
5 2 5 Ra c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
VCXO-Based Line Card Clock Synchronizer
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable,
jittery input clock and provide a de-jittered, low phase
noise output clock at a user determined frequency. The
device's clock multiplication ratios are user selectable
since all major PLL divider blocks can be configured
through device pin settings. External PLL loop filter
components allow tailoring of the VCXO PLL loop
response and therefore the clock jitter attenuation
characteristics.
The MK2069-01 is ideal for line card applications. Its
three input MUX enables selection of the master or
slave (backup) system clocks, as well as a backup
local line card clock. The lock detector (LD) output
serves as a clock status monitor. The clear (CLR) input
enables rapid synchronization to the phase of a newly
selected input clock, while eliminating the generation of
extra clock cycles and wander caused by memory in
the PLL feedback divider. CLR also serves as a
temporary holdover function when kept low.
Features
Input clock frequency of 1kHz to 170MHz
Output clock frequency of 500kHz to 160MHz
Jitter attenuation of input clock provided by VCXO
circuit. Jitter transfer characteristics user configured
through selection of external loop filter components.
3:1 Input MUX for input reference clocks
PLL lock status output
PLL Clear function allows seamless synchronizing to
an altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
VCXO-based clock generation offers very low jitter
and phase noise generation, even with a low
frequency or jittery input clock.
2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies
(TCLK).
Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
56 pin TSSOP package
Single 3.3V power supply
5V tolerant inputs on ICLK0 and ICLK1
Block Diagram
C ha rge
P um p
VC X O
Pu lla ble
x tal
V C L K
X 2
X 1
IS E T
4
V D D
4
C L R
L F
F V D iv id e r
1-40 96
R V
D ivid e r
1 ,2 ,4,1 28
SV
D ivid er
1,2 ,4 ,6,8,
1 0,12 ,16
IC L K 2
IC L K 1
M X 1:0
0X
R V1 :0
2
R T
D iv id er
1 -4
P h a se
D e tecto r
V C X O
P L L
F T D ivid er
1 -6 4
ST
D iv id e r
2 ,4 ,8 ,1 6
V C O
T ran slato r
P L L
S V 2:0
3
FV 1 1:0
F T 5 :0
6
ST 1 :0
2
T C L K
O E V
O E T
IC L K 0
10
01
2
L D
O E L
G N D
R C L K
O E R
L o ck D ete c to r
1 2
L D C
L D R
L F R
R T 1:0
2
Line Card Clock Synchronizer
MDS 2069-01 G
2
Revision 020503
I n t e g r a t e d C i r c u i t S y s t e m s
q
5 2 5 R a c e S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK2069-01
Pin Assignment
Input Selection Tables
Input Mux Selection Table
VCXO PLL Reference Divider Selection Table
VCXO PLL Feedback Divider Selection
VCXO PLL Scaling Divider Selection Table
Translator PLL Reference Divider Selection
Table
Translator PLL Feedback Divider Selection
Translator PLL Scaling Divider Selection Table
MX1 MX0
Input Selection
0
0
ICLK0
0
1
ICLK0
1
0
ICLK1
1
1
ICLK2
RV1 RV0
RV Divider Ratio
0
0
4
0
1
128
1
0
2
1
1
1
21
F V 0
22
F V 1
23
F V 2
24
F V 3
1
S T 0
2
S T 1
3
R T 0
4
R T 1
5
F T 0
6
F T 1
7
F T 2
8
F T 3
9
F T 4
10
F T 5
11
R V 0
12
V D D T
13
G N D T
14
X 1
15
V D D V
16
X 2
17
G N D V
18
L F R
19
L F
20
IS E T
25
F V 4
26
F V 5
27
F V 6
28
F V 7
36
35
34
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32
31
30
29
C L R
IC L K 0
IC L K 2
M X 1
S V 2
S V 1
S V 0
R V 1
M X 0
IC L K 1
O E L
O E T
O E V
O E R
V D D
L D
T C L K
V D D P
V C L K
G N D P
R C L K
L D R
G N D
L D C
F V 1 1
F V 1 0
F V 9
F V 8
M
K
2069-
01
FV11:0 FV Divider Ratio
Notes
0...00
2
For FV addresses 0 to 4094,
FV Divide = Address + 2
0...01
3
:
:
1...10
4096
1...11
1
SV2
SV1
SV0
SV Divider Ratio
0
0
0
4
0
0
1
6
0
1
0
8
0
1
1
10
1
0
0
12
1
0
1
2
1
1
0
16
1
1
1
1
RT1
RT0
RT Divider Ratio
0
0
2
0
1
3
1
0
4
1
1
1
FT5:0
FT Divider
Ratio
Notes
000000
2
For FT addresses 0 to 62,
FT Divide = Address + 2
000001
3
:
:
111110
64
111111
1
ST1
ST0
ST Divider Ratio
0
0
2
0
1
4
1
0
8
1
1
16
Line Card Clock Synchronizer
MDS 2069-01 G
3
Revision 020503
I n t e g r a t e d C i r c u i t S y s t e m s
q
5 2 5 R a c e S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK2069-01
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ST0
Input
Scaling Divider bit 0 input, Translator PLL (internal pull-up).
2
ST1
Input
Scaling Divider bit 1 input, Translator PLL (internal pull-up).
3
RT0
Input
Reference Divider bit 0 input, Translator PLL (internal pull-up).
4
RT1
Input
Reference Divider bit 1 input, Translator PLL (internal pull-up).
5
FT0
Input
Feedback Divider bit 0 input, Translator PLL (internal pull-up).
6
FT1
Input
Feedback Divider bit 1 input, Translator PLL (internal pull-up).
7
FT2
Input
Feedback Divider bit 2 input, Translator PLL (internal pull-up).
8
FT3
Input
Feedback Divider bit 3 input, Translator PLL (internal pull-up).
9
FT4
Input
Feedback Divider bit 4 input, Translator PLL (internal pull-up).
10
FT5
Input
Feedback Divider bit 5 input, Translator PLL (internal pull-up).
11
RV0
Input
Reference Divider bit 0 input, VCXO PLL (internal pull-up).
12
VDDT
Power
Power Supply connection for translator PLL.
13
GNDT
Ground
Ground connection for translator PLL.
14
X1
-
Crystal oscillator input. Connect this pin to the external reference crystal.
15
VDDV
Power
Power Supply connection for VCXO PLL.
16
X2
-
Crystal oscillator output. Connect this pin to the external reference crystal.
17
GNDV
Ground
Ground connection for VCXO PLL.
18
LFR
-
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
19
LF
-
Loop filter connection, active node. Refer to loop filter circuit on page 6.
20
ISET
-
Charge pump current setting input. Refer to loop filter circuit on page 6.
21
FV0
Input
Feedback Divider bit 0 input, VCXO PLL (internal pull-up).
22
FV1
Input
Feedback Divider bit 1 input, VCXO PLL (internal pull-up).
23
FV2
Input
Feedback Divider bit 2 input, VCXO PLL (internal pull-up).
24
FV3
Input
Feedback Divider bit 3 input, VCXO PLL (internal pull-up).
25
FV4
Input
Feedback Divider bit 4 input, VCXO PLL (internal pull-up).
26
FV5
Input
Feedback Divider bit 5 input, VCXO PLL (internal pull-up).
27
FV6
Input
Feedback Divider bit 6 input, VCXO PLL (internal pull-up).
28
FV7
Input
Feedback Divider bit 7 input, VCXO PLL (internal pull-up).
29
FV8
Input
Feedback Divider bit 8 input, VCXO PLL (internal pull-up).
30
FV9
Input
Feedback Divider bit 9 input, VCXO PLL (internal pull-up).
31
FV10
Input
Feedback Divider bit 10 input, VCXO PLL (internal pull-up).
32
FV11
Input
Feedback Divider bit 11 input, VCXO PLL (internal pull-up).
33
MX1
Input
Input MUX selection bit 1 (internal pull-up).
34
ICLK2
Input
Reference clock input 2.
35
ICLK0
Input
Reference clock input 0. 5V tolerant input.
36
CLR
Input
Clear input, clears VCXO PLL dividers when low (internal pull-up).
37
LDC
-
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
38
GND
Ground
Digital ground connection.
39
LDR
-
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
40
RCLK
Output
VCXO PLL phase detector Reference Clock output.
41
GNDP
Ground
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
Line Card Clock Synchronizer
MDS 2069-01 G
4
Revision 020503
I n t e g r a t e d C i r c u i t S y s t e m s
q
5 2 5 R a c e S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK2069-01
Functional Description
The MK2069-01 is a PLL (phase locked loop) based
clock generator that generates output clocks
synchronized to an input reference clock. It contains
two cascaded PLL's with user selectable divider ratios.
The first PLL is VCXO-based and uses an external
pullable crystal as part of the normal "VCO" (voltage
controlled oscillator) function of the PLL. The use of a
VCXO assures a low phase noise clock source even
when a low PLL loop bandwidth is implemented. A low
loop bandwidth is needed when the input reference
frequency is low, or when jitter attenuation of the input
reference is desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL which has a maximum
output frequency of 27 MHz. This second PLL, or
Translator PLL, uses an on-chip VCO circuit that can
provide an output clock up to 160 MHz. The Translator
PLL uses a high loop bandwidth (typically greater than
1 MHz) to assure stability of the VCO clock output. It
requires a stable, high frequency input reference which
is provided by the VCXO PLL.
The divide values of the divider blocks within both PLLs
are set by device pin configuration. This enables the
system designer to define the following:
Input clock frequency
VCXO crystal frequency
VCLK output frequency
RCLK output frequency, which is also the phase
detector frequency of the VCXO PLL.
TCLK output frequency
Any unused clock or logic outputs can be tri-stated to
reduce interference (jitter, phase noise) on other clock
outputs. Outputs can also be tri-stated for system
testing purposes.
External components are used to configure the VCXO
PLL loop response. This serves to maximize loop
stability and to achieve the desired input clock jitter
attenuation characteristics.
42
VCLK
Output
Clock output from VCXO PLL
43
VDDP
Power
Power Supply connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
44
TCLK
Output
Clock output from Translator PLL
45
LD
Output
Lock detector output.
46
VDD
Power
Power Supply connection for digital circuitry.
47
OER
Input
Output enable for RCLK. RCLK is tri-stated when low (internal pull-up).
48
OEV
Input
Output enable for VCLK. VCLK is tri-stated when low (internal pull-up).
49
OET
Input
Output enable for TCLK. TCLK is tri-stated and the translator PLL is disabled
when low (internal pull-up).
50
OEL
Input
Output enable for LD and LDR. Both are tri-stated when low (internal pull-up).
51
ICLK1
Input
Reference clock input 1. 5V tolerant input.
52
MX0
Input
Input MUX selection bit 0 input (internal pull-up).
53
RV1
Input
Reference Divider bit 1 input, VCXO PLL (internal pull-up).
54
SV0
Input
Scaler Divider bit 0 input, VCXO PLL (internal pull-up).
55
SV1
Input
Scaler Divider bit 1 input, VCXO PLL (internal pull-up).
56
SV2
Input
Scaler Divider bit 2 input, VCXO PLL (internal pull-up).
Pin
Number
Pin
Name
Pin
Type
Pin Description
Line Card Clock Synchronizer
MDS 2069-01 G
5
Revision 020503
I n t e g r a t e d C i r c u i t S y s t e m s
q
5 2 5 R a c e S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK2069-01
Application Information
The MK2069-01 is a mixed analog / digital integrated
circuit that is sensitive to PCB (printed circuit board)
layout and external component selection. Used
properly, the device will provide the same high
performance expected from a canned VCXO-based
hybrid timing device, but at a lower cost. To help avoid
unexpected problems, the guidance provided in the
sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
Where:
FV Divider = 1 to 4096
RV Divider = 1,2,4 or 128
The operational frequency range of VCLK is set by the
allowable frequency range of the external VCXO
crystal and by the internal VCXO divider selections:
Where:
F(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal
frequency between 13.5 MHz and 27 MHz is
recommended.
Because VCLK is generated by the external crystal, the
frequency range of VCLK in a given configuration is
limited to the pullable range of the crystal. This is
guaranteed to be +/-115 ppm minimum. This frequency
range in ppm also applies to the input clock and other
clock outputs if the device is to remain frequency
locked to the input, which is required for normal
operation.
Setting TCLK Output Frequency
The clock frequency of TCLK is determined by:
Where:
FT Divider = 1 to 64
RT Divider = 1 to 4
The frequency range of TCLK is set by the operational
range of the internal VCO circuit and the output divider
selections:
Where:
f(VCO) = 40 to 320 MHz
ST Divider = 2,4,8 or 16
A higher VCO frequency will generally produce lower
phase noise and therefore is preferred.
MK2069-01 Loop Response and JItter
Attenuation Characteristics
The MK2069-01 will reduce the transfer of phase jitter
existing on the input reference clock to the output
clock. This operation is known as jitter attenuation. The
low-pass frequency response of the VCXO PLL loop is
the mechanism that provides input jitter attenuation.
Clock jitter, more accurately called phase jitter, is the
overall instability of the clock period which can be
measured in the time domain using an oscilloscope, for
instance. Jitter is comprised of phase noise which can
be represented in the frequency domain. The phase
noise of the input reference clock is attenuated
according to the VCXO PLL low-pass frequency
response curve. The response curve, and thus the jitter
attenuation characteristics, can be established through
the selection of external MK2069-01 passive
components and other device setting as explained in
the following section.
f(VCLK)
FV Divider
RV Divider
----------------------------
f(ICLK)
=
f(VCLK)
f VCXO
(
)
SV Divider
-----------------------
=
f(TCLK)
FT Divider
RT Divider
----------------------------
f(VCLK)
=
f(TCLK)
f(VC0)
ST Divider
-----------------------
=