Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVMCOS DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- 2.5V AC Characteristics
- 2.5V/1.8V AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 2.5V Core/2.5V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- 3.3V Core/1.8V Output Load AC Test Circuit Diagram
- 2.5V Core/1.8V Output Load AC Test Circuit Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Input Skew Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
1
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS83052I-01 is a 2-bit, 2:1, Single-ended Mul-
tiplexer and a member of the HiPerClockSTM fam-
ily of High Performance Clock Solutions from ICS.
The ICS83052I-01 has two selectable single-ended
clock inputs and two single-ended clock outputs.
The output has a V
DDO
pin which may be set at 3.3V, 2.5V, or
1.8V, making the device ideal for use in voltage translation ap-
plications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug. Possible applications include systems with up to two
transceivers which need to be independently set for different
rates. For example, a board may have two transceivers, each
of which need to be independently configured for 1 Gigabit
Ethernet or 1 Gigabit Fibre Channel rates. Another possible
application may require the ports to be independently set for
FEC (Forward Error Correction) or non-FEC rates. The device
operates up to 250MHz and is packaged in a 16 TSSOP.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
2-bit, 2:1 single-ended multiplexer
Nominal output impedance: 15
(V
DDO
= 3.3V)
Maximum output frequency: 250MHz
Propagation delay: 2.5ns (typical)
Input skew: 45ps (typical)
Part-to-part skew: TBD
Additive phase jitter, RMS (12KHz - 20MHz):
0.07ps (typical)
Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40C to 85C ambient operating temperature
SEL0
CLK0
CLK1
SEL1
OE
Q0
Q1
0
1
0
1
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
nc
V
DDO
nc
GND
Q1
SEL1
CLK1
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
V
DDO
nc
GND
Q0
SEL0
CLK0
OE
ICS83052I-01
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
2
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
3
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 3.3V5%,
OR
2.5V5%,
OR
1.8V0.2V,
T
A
= -40C
TO
85C
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TO
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Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
4
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V 5%, T
A
= -40C
TO
85C
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T
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4C. LVCMOS/LVTTL DC C
HARACTERISTICS
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T
A
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TO
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l
o
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m
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3
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3
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2
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3
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3
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1
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2
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0
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1
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V
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D
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3
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0
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3
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V
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5
V
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2
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0
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5
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5
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3
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o
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3
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3
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0
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S
,
0
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V
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%
5
V
5
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2
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o
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3
.
3
=
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V
D
D
%
5
V
5
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2
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V
3
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3
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D
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;
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5
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2
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;
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2
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8
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0
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h
t
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m
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.
2
/
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
5
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 2.5V 5%, T
A
= -40C
TO
85C
l
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5C. AC C
HARACTERISTICS
,
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DD
= 3.3V 5%, V
DDO
= 1.8V 0.2V, T
A
= -40C
TO
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.
k
c
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:
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.
5
6
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h
T
:
5
E
T
O
N
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
6
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
T
ABLE
5D. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V 5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
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5E. AC C
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Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
7
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter (Random)
at 155.52MHz (12KHz - 20MHz)
= 0.07ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
8
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.40.065V
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
SCOPE
Qx
LVCMOS
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDO
-1.25V5%
V
DD
1.25V5%
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5 C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ART
-
TO
-P
ART
S
KEW
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
SCOPE
Qx
LVCMOS
1.6V0.025V
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
V
DD
,
V
DDO
GND
V
DD
,
V
DDO
GND
GND
GND
GND
tsk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
Part 1
Part 2
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
9
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0, Q1
tp
LH
V
DDO
2
V
DD
2
CLK0, CLK1
Q0, Q1
I
NPUT
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PD1
t
PD2
CLKx
Q0, Q1
CLKy
Q0, Q1
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
10
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83052I-01 is: 967
T
ABLE
5.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
11
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
6. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
6
1
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
4
0
1
.
5
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Integrated
Circuit
Systems, Inc.
83052AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
12
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
PRELIMINARY
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
r
e
b
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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