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Электронный компонент: 307G-03LF

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ICS307-03
MDS 307-03 C
1
Revision 101705
I n t e gra t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Description
The ICS307-03 is a dynamic, serially programmable
clock source which is flexible and takes up minimal
board space. Output frequencies are programmed via
a 3-wire SPI port.
An advanced PLL coupled to an array of configurable
output dividers and three outputs allows low-jitter
generation of frequencies from 200 Hz to 270 MHz.
The device can be reprogrammed during operation,
making it ideal for applications where many different
frequencies are required, or where the output
frequency must be determined at run time. Glitch-free
frequency transitions, where the clock period changes
slightly over many cycles, are possible.
Features
Crystal or clock reference input
3.3 V CMOS outputs
Three outputs can be individually configured or shut
off
Small 16-pin TSSOP package
Reprogrammable during operation
3-wire SPI serial interface
Glitch-free output frequency switching
User selectable charge pump current and damping
resistor
Power-down control via hardware pin or software
control bit
Programming word can be generated by ICS
VersaClock II Software
Directly programmable via VersaClock II Software
and a Windows PC parallel port
Available in Pb (lead) free package
Block Diagram
REF Divide
1-2055
VCO DIVIDE
12-2055
Resistor
(Table 4)
Charge Pump
(Table 3)
(Table 2)
(Table 5)
CLK1
[Bit 110]
[Bit 123]
[Bit 124]
[Bit 129]
[Bit 111]
CLK2
CLK3
(Table 7)
Divider
2 - 8232
(Table 1)
X1
X2
[Bit 122]
Divider
2 - 34
Divider
2 - 34
(Table 6)
1
0
1
0
11pF
300
pF
CP
Programming
Register
(132 bits)
DIN
CS
SCLK
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
2
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Pin Assignment
Pin Descriptions
12
1
11
2
10
3
9
X1
4
VDD
5
VDD
6
PD
7
VDD
8
GND
CLK3
GND
CLK2
GND
DIN
SCLK
GND
CS
16
15
14
13
CLK1
X2
16-pin TSSOP
IC
S
3
0
7
-0
3
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
XI
Connect to input reference clock or crystal.
2
VDD
Power
Power connection for crystal oscillator.
3
VDD
Power
Power connection for PLL.
4
VDD
Power
Power connection for inputs and outputs.
5
GND
Power
Ground connection for crystal oscillator.
6
GND
Power
Ground connection for PLL.
7
GND
Power
Ground connection for inputs and outputs.
8
CLK1
Output
Clock 1 output.
9
SCLK
Input
Programming interface - Serial clock input. Internal pull-up.
10
CS
Input
Programming interface - LOAD input. Internal pull-down.
11
DIN
Input
Programming interface - Serial data input. Internal pull-up.
12
CLK2
Output
Clock 2 output.
13
GND
Power
Ground connection.
14
CLK3
Output
Clock 3 output.
15
PD
Input
Crystal, PLL, and outputs are powered-down when low. Internal pull-up.
16
X2
-
Connect to crystal. Leave open if reference clock input is used.
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
3
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Table 1. Input Divider
Table 2. VCO Divider
Divide Value
12
11
10
9
8
7
Bits
6
5
4
3
2
1
0
Rule
1
X
X
X
X
X
X
X
X
X
X
X
0
0
1+ Bit 0
2
X
X
X
X
X
X
X
X
X
X
X
0
1
1 + Bit 0
3
X
X
X
X
X
X
X
1
1
1
0
1
0
subtract 2 from the
desired value, convert to
binary, invert, and apply
to bits 5...2
Bits [1..0] = 10
4
X
X
X
X
X
X
X
1
1
0
1
1
0
5
X
X
X
X
X
X
X
1
1
0
0
1
0
6
X
X
X
X
X
X
X
1
0
1
1
1
0
7
X
X
X
X
X
X
X
1
0
1
0
1
0
8
X
X
X
X
X
X
X
1
0
0
1
1
0
9
X
X
X
X
X
X
X
1
0
0
0
1
0
10
X
X
X
X
X
X
X
0
1
1
1
1
0
11
X
X
X
X
X
X
X
0
1
1
0
1
0
12
X
X
X
X
X
X
X
0
1
0
1
1
0
13
X
X
X
X
X
X
X
0
1
0
0
1
0
14
X
X
X
X
X
X
X
0
0
1
1
1
0
15
X
X
X
X
X
X
X
0
0
1
0
1
0
16
X
X
X
X
X
X
X
0
0
0
1
1
0
17
X
X
X
X
X
X
X
0
0
0
0
1
0
18
0
0
0
0
0
0
0
1
0
1
0
1
1
subtract 8 from the
desired divide value,
convert to binary, and
apply to bits 11...2
Bits [1..0] = 11
19
0
0
0
0
0
0
0
1
0
1
1
1
1
20
0
0
0
0
0
0
0
1
1
0
0
1
1
21
0
0
0
0
0
0
0
1
1
0
1
1
1
...
2054
1
1
1
1
1
1
1
1
1
1
0
1
1
2055
1
1
1
1
1
1
1
1
1
1
1
1
1
Bits
Divide Value
23
22
21
20
19
18
17
16
15
14
13
Rule
12
0
0
0
0
0
0
0
0
1
0
0
subtract 8 from the desired
divide value, convert to
binary, and apply to bits
23...13
13
0
0
0
0
0
0
0
0
1
0
1
14
0
0
0
0
0
0
0
0
1
1
0
...
2054
1
1
1
1
1
1
1
1
1
1
0
2055
1
1
1
1
1
1
1
1
1
1
1
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
4
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Table 3. Charge Pump Current
Table 4. Loop Filter Resistor
Bits
Charge Pump Current (
A)
93
92
91
127
128
Rule
1.25
1
1
1
0
0
Icp = ([127...128]+1)*1.25
A*([93 92 91] + 1)
2.5
1
1
0
0
0
2.5
1
1
1
1
0
3.75
1
0
1
0
0
3.75
1
1
1
0
1
5
1
0
0
0
0
5
1
1
0
1
0
5
1
1
1
1
1
6.25
0
1
1
0
0
7.5
0
1
0
0
0
7.5
1
1
0
0
1
7.5
1
0
1
1
0
70
0
0
1
0
0
10
0
0
0
0
0
10
1
0
0
1
0
10
1
1
0
1
1
11.25
1
0
1
0
1
12.5
0
1
1
1
0
15
1
0
0
0
1
15
0
1
0
1
0
15
1
0
1
1
1
17.5
0
0
1
1
0
18.75
0
1
1
0
1
20
0
0
0
1
0
20
1
0
0
1
1
22.5
0
1
0
0
1
25
0
1
1
1
1
26.25
0
0
1
0
1
30
0
0
0
0
1
30
0
1
0
1
1
35
0
0
1
1
1
40
0
0
0
1
1
Bits
Resistor Value
89
90
64 k
0
0
52 k
0
1
16 k
1
0
4 k
1
1
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
5
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Table 5. Output Divider for Output 1
Divide
Value
109 108 107 106 105 104 103
Bits
102
101 100
99
98
97
96
95
Rule
2
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
3
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
4
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
5
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
6
X
X
X
X
X
X
X
X
X
X
X
1
0
0
1
7
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
8
X
X
X
X
X
X
X
1
1
1
0
1
1
0
0
apply Rule from Divide Values 14-37
9
X
X
X
X
X
X
X
X
X
X
1
0
0
1
1
10
X
X
X
X
X
X
X
1
1
0
1
1
1
0
0
apply Rule from Divide Values 14-37
11
X
X
X
X
X
X
X
X
X
X
0
1
0
1
1
12
X
X
X
X
X
X
X
1
1
0
0
1
1
0
0
apply Rule from Divide Values 14-37
13
X
X
X
X
X
X
X
X
X
X
1
1
0
1
1
14
X
X
X
X
X
X
X
1
0
1
1
1
1
0
0
subtract 6 from the desired
divide value, convert to binary,
invert, and apply to bits 102..98
set bits [97..95] = 100
15
X
X
X
X
X
X
X
1
0
1
1
0
1
0
0
36
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
37
X
X
X
X
X
X
X
0
0
0
0
0
1
0
0
38
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
output divide =
((([109..101]+3)*2)+[98])*2^[100
39
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
...
(increments of 1)
set bits [95..97] = 101
1029
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
(
this Rule applies to Divide
Values 38-8232)
1030
0
1
1
1
1
1
1
1
0
0
1
0
1
0
1
1032
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
...
(increments of 2)
2056
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2058
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
2060
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
2064
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
...
(increments of 4)
4112
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
4116
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
4120
0
1
1
1
1
1
1
1
0
1
1
0
1
0
1
4128
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
...
(increments of 8)
8224
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
8232
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
6
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Table 6. Output Divider for Output 2
Table 7. Output Divider for Output 3
Bits
Divide Value
117
116
115
114
113
Rule
2
1
1
1
1
0
output divide = ([117..114]+2)*2^[113])
4
1
1
1
1
1
6
1
1
1
0
1
8
1
1
0
1
1
10
1
1
0
0
1
12
1
0
1
1
1
14
1
0
1
0
1
16
1
0
0
1
1
18
1
0
0
0
1
20
0
1
1
1
1
22
0
1
1
0
1
24
0
1
0
1
1
26
0
1
0
0
1
28
0
0
1
1
1
30
0
0
1
0
1
32
0
0
0
1
1
34
0
0
0
0
1
Bits
Divide Value
121
120
119
118
94
Rule
2
1
1
1
1
0
output divide = ([121..118]+2)*2^[94])
4
1
1
1
1
1
6
1
1
1
0
1
8
1
1
0
1
1
10
1
1
0
0
1
12
1
0
1
1
1
14
1
0
1
0
1
16
1
0
0
1
1
18
1
0
0
0
1
20
0
1
1
1
1
22
0
1
1
0
1
24
0
1
0
1
1
26
0
1
0
0
1
28
0
0
1
1
1
30
0
0
1
0
1
32
0
0
0
1
1
34
0
0
0
0
1
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
7
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Table 8. Miscellaneous Control Bits
External Components
The ICS307-03 requires a minimum number of external components for proper operation.
Decoupling Capacitors
TheICS307-03 requires 0.01
F decoupling capacitors to be connected between each VDD pin and the Ground
Plane. The 0.01
F capacitors must be placed as close to the ICS307-03's power pins as possible to minimize lead
inductance.
Output Termination
The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation
with single ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50
Ohm transmission line without the need for any series resistors.
Crystal Selection
A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of 12 C should be used. For
crystals with a specified load capacitance greater than 12, additional crystal capacitors may be connected from
each of the pins X1 and X2 to ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal
caps should be = (C
L
-12)*2, where C
L
is the crystal load capacitance in pF and C is the capacitance value from
Table 4.
For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.
Bit
Function
24~88
Reserved--set to 0
110
OE1--set to 1 to enable CLK1
111
OE2--set to 1 to enable CLK2
112
1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO
122
Crystal Input = 1, Clock Input = 0
123
Selects source for CLK2 (see block diagram)
124
Selects source for CLK3 (see block diagram)
125
Reserved--set to 0
126
Reserved--set to 0
129
OE3--set to 1 to enable CLK3
130
Reserved--set to 0
131
Reserved--set to 0
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
8
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Initial Output Frequency
ICS307-03 on-chip registers are initially configured to provide a 1x output clock on the CLK1 output, and 0.5x clock
on CLK2 and CLK3. The output frequency will be the same as the input clock or crystal for input frequencies from
10 - 50 MHz. This is useful when the ICS307-03 needs to provide an initial system clock at power-up.
Determining and Controlling the Output Frequency with VersaClock
TM
II
The ICS307-03 is directly supported by the ICS provided software called VersaClock II. Complete programming
words for this device can be calculated on any Windows PC by running the VersaClock II software and simple
inputting desired input and output frequencies. Once the software generates an appropriate programming word, it
may then be either copied to the Windows clipboard or even directly programmed into the ICS307-03 via the host
computers parallel port.
For more information on VersaClock II, please visit www.icst.com or send an e-mail to ics-mk@icst.com.
Manually Determining the Output Frequency
The user has full control over the desired output frequency as long as it is operated within the limits shown in the
AC Electrical Characteristics.
The output of the ICS307-03 can be determined by the following equation:
Where:
VCO Divider (V) = 12 to 2055
Reference Divider Word (R) = 1 to 2055
Output Divider = values in tables 5, 6, 7
Also, the following operating ranges should be observed.
To determine the best combination of VCO, reference, and output dividers, please use the VersaClock II software
mentioned above. If more information is needed, please contact ICS by sending an e-mail to ics-mk@icst.com.
CLK1Frequency
InputFrequency
V
R OD
------------------
=
VCOmin InputFrequency V
R
---- VCOmaxfreq
<
<
20kHz Input Frequency
R
------------------------------------------- 100MHz
<
<
S
ERIALLY
P
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C
LOCK
S
OURCE
MDS 307-03 C
9
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Programming Interface
The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time
after power is properly applied. If V or R values are changed, the frequency will transition smoothly to the
new value without glitches or short cycles. However, changing any divider or mux in the output signal path
may generate a glitch.
The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data bit
value in the rising edge of It latches the most recently shifted 132 bit values into the control register of
device whenever CS is high. Care must be taken to ensure that CS is always low until the system is ready
to load in a new register value and that SCLK is never toggled high when CS is high.
The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit
112 held low) with the waveform and timing shown below:.
Figure 2: ICS307-03 Programming Timing Diagram
Table 8: AC Parameters for Programming the ICS307-03
Programming with VersaClock Software
The VersaClock II Software not only generates the programming word for the user, it can also be used to program
the device via the host computer's parallel port. Demonstration boards are available from ICS that allows the
VersaClock II S/W to directly connect the ICS307-03 to a Windows based PC's DB-25 parallel port connector and
programmed simply by pressing the "Program Part" button.
Contact ics-mk@icst.com for more details.
Parameter
Condition
Min. Max.
Units
t
SETUP
Setup time
2.5
ns
t
HOLD
Hold time after SCLK
2.5
ns
t
W
Data wait time
2.5
ns
t
S
Strobe pulse width
10
ns
SCLK Frequency
200
MHz
128
129
130
131
1
0
t
hold
t
setup
2
SCLK
CS
t
s
t
w
DIN
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
10
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS307-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability.
Electrical parameters are guaranteed only over the recommended operating temperature range.
Recommended Operating Conditions
DC Electrical Characteristics
VDD=3.3 V 5% , Ambient temperature 0 to +70
C, unless stated otherwise
Item
Rating
Supply Voltage, VDD
5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Storage Temperature
-65 to +150
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
3.6
V
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Output High Voltage
V
OH
I
OH
= -4 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 4 mA
0.4
V
Output High Voltage,
CMOS level
V
OH
I
OH
= -6.5 mA
VDD-0.4
V
Tri-state Output Leakage
1
A
Operating Supply Current
IDD
27 MHz crystal
No load, 100 MHz out,
all outputs enabled
24
mA
Short Circuit Current
CLK outputs
60
mA
Input Capacitance
C
IN
4
pF
On-Chip Pull-up Resistor
R
PU
240
k
On-Chip Pull-down
Resistor
R
PD
100
k
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
11
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
AC Electrical Characteristics
VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C, unless stated otherwise
Note 1: Measured with 15 pF load.
Note 2: Jitter performance will change depending on configuration settings.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
Fundamental crystal
3
27
MHz
Clock
0.1
300
MHz
Clock Output Frequency
F
OUT
5 pF load
0.0002
270
MHz
15 pF load
0.0002
200
MHz
Output Clock Rise/Fall Time
t
R,
t
F
20 to 80% (5 pF load)
1.5
ns
Output Clock Duty Cycle
Output Divides <> 3
45
49-51
55
%
Output Divide = 3
40
60
%
Frequency Transition time
STROBE high to CLK
out
3
10
ms
One Sigma Clock Period Jitter
Note 2
50
ps
Maximum Absolute Jitter
t
ja
Deviation from mean,
Note 2
120
ps
VCO Frequency
VCO
F
100
730
MHz
Divider 1 Input
Output divider 1 = 2
(5 pF load)
540
MHz
Output divider 1 = 2
(15 pF load)
400
MHz
Output divider 1 = 3
(5 pF load)
720
MHz
Output divider 1 = 3
(15 pF load)
600
MHz
Output divider 1 = 38
~ 1029
570
MHz
All other Output
Divider 1 values
730
MHz
Divider 2 and 3 Inputs
Output divider 2, 3 = 2
(5 pF load)
540
MHz
Output divider 2, 3 = 2
(15 pF load)
400
MHz
Output divider 2, 3=12
440
MHz
Output divider 2, 3 =
16, 24, 28 and 32
500
MHz
All other Output
Divider 2 & 3 values
730
MHz
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
MDS 307-03 C
12
Revision 101705
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS307-03
Package Outline and Package Dimensions
(16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping packaging
Package
Temperature
ICS307G-03
ICS307G-03
Tubes
16-pin TSSOP
0 to +70
C
ICS307G-03T
ICS307G-03
Tape and Reel
16-pin TSSOP
0 to +70
C
ICS307G-03LF
307G-03LF
Tubes
16-pin TSSOP
0 to +70
C
ICS307G-03LFT
307G-03LF
Tape and Reel
16-pin TSSOP
0 to +70
C
IN D E X
A R E A
1 2
16
D
E 1
E
S E A T IN G
P LA N E
A
1
A
A
2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004