Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- Differential DC Characteristics
- LVHSTL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Schematic Example
- Clock Input Interface
- CLK/nCLK Input Driven by HiPerClockS LVHSTL Driver Diagram
- CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagrams
- CLK/nCLK Input Driven by 3.3V LVPECL Driver w/AC Couple Diagram
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVHSTL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
1
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
G
ENERAL
D
ESCRIPTION
The ICS85211I-03 is a low skew, high perfor-
mance 1-to-2 Differential-to-LVHSTL Fanout
Buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels.The ICS85211I-03 is char-
acterized to operate from a 3.3V power supply. Guar-
anteed output and part-to-part skew characteristics
make the ICS85211I-03 ideal for those clock distribution
applications demanding well defined performance and
repeatability. For optimal performance, terminate all outputs.
F
EATURES
2 differential LVHSTL compatible outputs
1 differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any single-ended input signal to
LVHSTL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1ns (maximum)
Output duty cycle: 49% - 51% up to 266.6MHz
V
OH
= 1V (maximum)
3.3V operating supply
-40C to 85C ambient operating temperature
HiPerClockSTM
,&6
ICS85211I-03
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
V
DD
CLK
nCLK
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
2
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
3
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, T
A
= -40C
TO
85C
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DC C
HARACTERISTICS
,
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DD
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TO
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
DD
-0.5V to V
DD
+ 0.5 V
Outputs, V
DD
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
4
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, T
A
= -40C
TO
85C
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N
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
5
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0, nQ1
Q0, Q1
t
PD
nCLK
CLK
nQ0, nQ1
Q0, Q1
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
odc & t
P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
tsk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
nCLK
CLK
GND
V
DD
SCOPE
LVHSTL
Qx
nQx
V
DD
=
3.3V5%
GND = 0V
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
6
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 2 shows a schematic example of ICS85211I-03. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
F
IGURE
2. ICS85211I-03 LVHSTL B
UFFER
S
CHEMATIC
E
XAMPLE
near the power pin. For ICS85211I-03, the unused outputs need
to be terminated.
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
R4
50
U1
ICS85211-03
1
2
3
4
8
7
6
5
Q0
nQ0
Q1
nQ1
VDD
CLK
nCLK
GND
R6
50
C1
0.1u
HiPerClockS
Unused
Output
Need To
Be
Terminated
1.8V
LVHSTL Input
+
-
Zo = 50 Ohm
R1
50
ICS
R5
50
LVHSTL
R2
50
Zo = 50 Ohm
LVHSTL Driv er
VDD=3.3V
R3
50
Zo = 50 Ohm
Zo = 50 Ohm
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
7
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts differential input signals of both V
SWING
and V
OH
to meet the V
PP
and V
CMR
input requirements.
Figures 3 to
6 show interface examples for the ICS85211I-03 clock input driven
by most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
F
IGURE
3. ICS85211I-03 CLK/
N
CLK I
NPUT
D
RIVEN
BY
H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
driver components to confirm the driver termination requirement.
For example in
Figure 3, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
F
IGURE
4. ICS85211I-03 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
(I
NTERFACE
1)
F
IGURE
5. ICS85211I-03 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
(I
NTERFACE
2)
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
F
IGURE
6. ICS85211I-03 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
R3
125
LVPECL
R1
84
C1
R2
84
HiPerClockS
CLK
nCLK
R5,R6 loc ate near the driv er pin.
Zo = 50 Ohm
3.3V
3.3V
C2
R4
125
R6
100-200
Zo = 50 Ohm
R5
100-200
3.3V
Input
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
8
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211I-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211I-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 50mA = 173.3mW
Power (outputs)
MAX
= 73.82mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 73.82mW = 147.6mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.3mW + 147.6mW = 320.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.321W * 103.3C/W = 118.2C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE
q
JA
FOR
8-
PIN
SOIC, F
ORCED
C
ONVECTION
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
9
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 7.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1.0V/50
) * (3.465V - 1.0V) = 49.3mW
Pd_L = (0.4V (50
) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 73.82mW
F
IGURE
7. LVHSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DD
V
OUT
RL
50
Q1
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
10
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85211I-03 is: 411
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
11
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
L
O
B
M
Y
S
s
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t
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85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
12
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional
processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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85211AMI-03
www.icst.com/products/hiperclocks.html
REV. B APRIL 8, 2003
13
Integrated
Circuit
Systems, Inc.
ICS85211I-03
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
E
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