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Электронный компонент: 7151M50L

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ICS7151
MDS 7151 E
1
Revision 012306
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
Spread Spectrum Clock Generator
Description
The ICS7151-10, -20, -40, and -50 are clock
generators for EMI (Electro Magnetic Interference)
reduction (see below for frequency ranges and
multiplier ratios). Spectral peaks can be attenuated by
slightly modulating the oscillation frequency. Both down
and center spread profiles are selectable. Down spread
maintains an average frequency less than an unspread
clock, and will not exceed the maximum frequency of
an unspread clock.
Features
Operating voltage of 3.3 V 0.3 V
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Input frequency range of 16.5 to 33.4 MHz
Output frequency ranges of 8.3 to 16.7 MHz, 16.5 to
33.4 MHz, 33.3 to 66.7 MHz, 66.6 to 133.4 MHz
Provides a spread spectrum clock output (0.5%,
1.5% center spread; -1.0%, -3.0% down spread)
Multiplication rates of x1/2, x1, x2, and x4
Advanced, low-power CMOS process
Block Diagram
Product Lineup
Product
Input Frequency Range
Multiplier Ratio
Output Frequency Range
ICS7151M-10, ICS7151MI-10
16.5 MHz to 33.4 MHz
X1
16.5 MHz to 33.4 MHz
ICS7151M-20, ICS7151MI-20
16.5 MHz to 33.4 MHz
X2
33.3 MHz to 66.7 MHz
ICS7151M-40, ICS7151MI-40
16.5 MHz to 33.4 MHz
X4
66.6 MHz to 133.4 MHz
ICS7151M-50, ICS7151MI-50
16.5 MHz to 33.4 MHz
X1/2
8.3 MHz to 16.7 MHz
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
S1:0
ENS
CKOUT
2
GND
VDD
Clock Buffer/
Crystal
Ocsillator
XIN
XOUT
External caps required with crystal for
accurate tuning of the clock
Spread Spectrum Clock Generator
MDS 7151 E
2
Revision 012306
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS7151
Pin Assignment
Spread Direction and Percentage
Select Table
Notes:
1. The modulation rate varies with input frequency.
2. Spread will default to ON when ENS pin is left open.
Pin Descriptions
XOUT
GND
S0
VDD
S1
CKOUT
ENS
XIN
1
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
S1
Pin 4
(note1)
S0
Pin 3
(note1)
Spread
Direction
Spread
Percentage (%)
0
0
Center
1.5
0
1
Center
0.5
1
0
Down
-1.0
1
1
Down
-3.0
ENS
(note 2)
Spread Spectrum
0
OFF
1
ON
Pin
Number
Pin
Name
Pin Type
Pin Description
1
XIN
Input
Resonator connection pin/clock input pin.
2
GND
Power
Connect to ground.
3
S0
Input
Select pin 0. Modulation rate setting pin.
4
S1
Input
Select pin 1. Modulation rate setting pin.
5
CKOUT
Output
Modulated clock output pin.
6
ENS
Input
Modulation enable setting pin. Internal pull-up resistor.
7
VDD
Power
Connect to +3.3 V.
8
XOUT
Output
Resonator connection pin.
Spread Spectrum Clock Generator
MDS 7151 E
3
Revision 012306
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS7151
External Components
The ICS7151 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between GND and VDD on pin 7, as close to this pin as
possible. For optimum device performance, the
decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
Series termination should be used on the clock output.
To series terminate a 50
trace (a commonly used
trace impedance) place a 27
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
25
.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 27
series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS7151. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Spread Spectrum Profile
The ICS7151 low EMI clock generator uses a triangular
frequency modulation profile for optimal down stream
tracking of zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant with
variations of the input frequency.
Time
F
r
eq
ue
nc
y
Modulation Rate
Spread Spectrum Clock Generator
MDS 7151 E
4
Revision 012306
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS7151
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS7151. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Overshoot/Undershoot
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs (referenced to GND)
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85
C
Storage Temperature
-55 to +125
C
Junction Temperature
-40 to +125
C
Soldering Temperature
260
C
Overshoot (V
IOVER
)
VDD + 1.0 V (t
OVER
< 50 ns)
Undershoot (V
IUNDER
)
GND - 1.0 V (t
UNDER
< 50 ns)
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.0
3.3
3.6
V
Input pin
V
IOVER
< V
DD
+ 1.0 V
V
IUNDER
< GND - 1.0 V
t
OVER
< 50 ns
t
UNDER
< 50 ns
V
DD
GND
Spread Spectrum Clock Generator
MDS 7151 E
5
Revision 012306
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS7151
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 0.3 V, Ambient Temperature -40 to +85
C
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 0.3 V, Ambient Temperature -40 to +85
C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
3.3
3.6
V
Supply Current
IDD
No load, at 3.3 V
10
20
mA
Input High Voltage
V
IH
XIN, S0, S1, ENS
VDDx0.8
VDD + 0.3
V
Input Low Voltage
V
IL
XIN, S0, S1, ENS
0.0
VDDx0.20
V
Output High Voltage
V
OH
CKOUT, I
OH
= -4 mA
2.0
V
Output Low Voltage
V
OL
CKOUT, I
OL
= 4 mA
0.4
V
Input Capacitance
C
IN
XIN, S0, S1, ENS
16
pF
Load Capacitance
C
L
CKOUT, 8.3 to 66.7
MHz
15
pF
CKOUT, 66.7 to 100
MHz
10
pF
CKOUT, 100 to 133.4
MHz
7
pF
Input Pull-up Resistor
R
PU
ENS
100
240
400
k
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Crystal Frequency
16.5
33.4
MHz
Input Clock Frequency
f
IN
16.5
33.4
MHz
Output Frequency
f
OUT
CKOUT, Multiply by 1
(ICS7151-10)
16.5
33.4
MHz
CKOUT, Multiply by 2
(ICS7151-20)
33.3
66.7
MHz
CKOUT, Multiply by 4
(ICS7151-40)
66.6
133.4
MHz
CKOUT, 2-frequency
division (ICS7151-50)
8.3
16.7
MHz
Input Clock Duty Cycle
XIN, 16.5 to 33.4 MHz
40
50
60
%
Output Clock Duty Cycle
t
DCC
CKOUT, 1.5 V
40
60
%
Output Slew Rate
CKOUT, 0.4 to 2.4 V,
CL = 15 pF
0.5
3.0
V/ns