8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8304 is a low skew, 1-to-4 Fanout
Buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions
from ICS. The ICS8304 is characterized at
full 3.3V for input V
DD
, and mixed 3.3V and
2.5V for output operating supply modes (V
DDO
). Guaran-
teed output and part-to-part skew characteristics make
t h e I C S 8 3 0 4 i d e a l f o r t h o s e c l o c k d i s t r i b u t i o n
applications demanding well defined performance and
repeatability.
F
EATURES
4 LVCMOS / LVTTL outputs
LVCMOS clock input
Maximum output frequency up to 166MHz
Output skew: 45ps (maximum at 3.3V supply)
Part-to-part skew: 500ps (maximum)
Small 8 lead SOIC package saves board space
3.3V input, outputs may be either 3.3V or 2.5V supply modes
0C to 70C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8304
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
V
DDO
V
DD
CLK
GND
1
2
3
4
Q0
Q1
Q2
Q3
CLK
HiPerClockSTM
,&6
Q3
Q2
Q1
Q0
8
7
6
5
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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r
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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HARACTERISTICS
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DD
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DDO
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A
= 0C
TO
70C
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2
/
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
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A
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8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
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ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
SCOPE
Qx
LVCMOS
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
-1.65V5%
GND
V
DD,
V
DDO
1.65V5%
SCOPE
Qx
LVCMOS
V
DD
V
DDO
3.3V/2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
2.05V5%
GND
1.25V5%
-1.25V5%
P
ARAMETER
M
EASUREMENT
I
NFORMATION
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
30%
70%
70%
30%
t
R
t
F
O
UTPUT
S
KEW
Qx
Qy
tsk(o)
P
ART
-
TO
-P
ART
S
KEW
Qx
Qy
PART 1
PART 2
tsk(pp)
V
DDO
/2
V
DDO
/2
V
DDO
/2
V
DDO
/2
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
t
PW
& t
P
ERIOD
P
ROPAGATION
D
ELAY
CLK
Q0:Q3
t
PD
V
DD
2
V
DDO
2
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
Q0:Q3
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
RANSISTOR
C
OUNT
The transistor count for ICS8304 is: 416
T
ABLE
5.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
6. P
ACKAGE
D
IMENSIONS
- S
UFFIX
M
Reference Document: JEDEC Publication 95, MS-012
P
ACKAGE
O
UTLINE
- S
UFFIX
M
L
O
B
M
Y
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0
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2
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3
3
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8
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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0
8304AM
www.icst.com/products/hiperclocks.html
REV. D APRIL 4, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
E
E
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