Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Description
- Pin Characteristics
- Control Input Function Table
- CLK_EN Timing Diagram
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- 3.3V Core/1.8V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Part-toPart Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Differential Clock Input Interface
- HiPerClockS CLK/nCLK Input Driven by ICS HiPerClockS LVHSTL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagrams
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVDS Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver w/AC Couple Diagram
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensinos
- Ordering Information
- Revision History Sheet
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
1
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8305I has selectable clock inputs that accept
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A sepa-
rate output enable pin controls whether the outputs are in the
active or high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
GND
OE
V
DD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
DDO
Q1
GND
Q2
V
DDO
Q3
GND
ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
F
EATURES
4 LVCMOS/LVTTL outputs
Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Maximum output frequency: 350MHz
Output skew: 40ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
3.3V core, 3.3V, 2.5V or 1.8V output operating supply
-40C to 85C ambient operating temperature
Lead-Free package fully RoHS compliant
LVCMOS_CLK
CLK
nCLK
CLK_SEL
Q0
Q1
Q2
Q3
0
1
CLK_EN
OE
D
Q
LE
0
1
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
2
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
3
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
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F
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T
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IAGRAM
Enabled
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Q0:Q3
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
4
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= -40C
TO
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2
/
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
5
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= -40C
TO
85C
l
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Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
6
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 1.8V -0.15V, T
A
= -40C
TO
85C
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
DDO
= 2.5V 5%, T
A
= -40C
TO
85C
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F
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
7
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Input/Output Additive
Phase Jitter
at 155.52MHz
= 0.04ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dB
c
/
H
Z
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
8
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
tsk(pp)
V
DDO
2
V
DDO
2
Qx
Qy
PART 1
PART 2
-1.65V5%
1.65V5%
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
-1.25V5%
1.25V5%
SCOPE
Qx
LVCMOS
-0.9V0.075V
0.9V0.075V
V
DD
V
DDO
2.4V0.09V
SCOPE
Qx
LVCMOS
V
DD
V
DDO
2.05V5%
V
DD
,
V
DDO
GND
GND
GND
Integrated
Circuit
Systems, Inc.
8305AGI
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REV. B MAY 19, 2005
9
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
nCLK
CLK
Q0:Q3
t
PD
V
DDO
2
V
DD
2
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0:Q3
LVCMOS_CLK
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
10
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
11
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
3E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
12
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8305I is: 459
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
LVCMOS Receiv er
R1
43
VDD
R5
1K
LVCMOS Receiv er
VDD=3.3V
VDD
R4
1K
Zo = 50
(U1,11)
Ro ~ 7 Ohm
3,.3V LVCMOS
(U1,15)
(U1,3)
VDD
R3
43
R2
43
C2
0.1u
U1
ICS8305
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
GND
Q3
VDDO
Q2
GND
Q1
VDDO
Q0
Zo = 50
VDD
Zo = 50
C1
0.1u
R6
1K
C3
0.1u
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using
ICS8305I LVCMOS buffer.
Figure 4 shows a schematic example
of the ICS8305I LVCMOS clock buffer. In this example, the input
F
IGURE
4. E
XAMPLE
ICS8305I LVCMOS C
LOCK
O
UTPUT
B
UFFER
S
CHEMATIC
is driven by an LVCMOS driver. CLK_EN is set at logic low to
select LVCMOS_CLK input.
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
13
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
14
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
Integrated
Circuit
Systems, Inc.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
15
ICS8305I
L
OW
S
KEW
, 1-
TO
-4, M
ULTIPLEXED
D
IFFERENTIAL
/
LVCMOS-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
E
E
H
S
Y
R
O
T
S
I
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