Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Output Enable & Clock Enable Function Table
- Enable Timing Diagram
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- Power Supply 1.8V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- Power Supply 3.3V/1.8V DC Characteristics
- Power Supply 2.5V/1.8V DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- 1.8V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- 2.5V/1.8V AC Characteristics
- Typical Phase Noise Plot at 25MHz (2.5V)
- Typical Phase Noise Plot at 25MHz (3.3V)
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 2.5V Core/2.5V Output Load AC Test Circuit Diagram
- 1.8V Core/1.8V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- 3.3V Core/1.8V Output Load AC Test Circuit Diagram
- 2.5V Core/1.8V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Crystal Input Interface
- Layout Guideline
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
1
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83905I is a low skew, 1-to-6 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance Clock
S o l u t i o n s f r o m I C S. T h e l ow i m p e d a n c e
LVCMOS/LVTTL outputs are designed to drive
50W series or parallel terminated transmission lines. The ef-
fective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply mode. Guaranteed output and part-to-part skew
characteristics along with the 1.8V output capabilities makes
the ICS83905I ideal for high performance, single ended appli-
cations that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 LVCMOS / LVTTL outputs
Outputs able to drive 12 series terminated lines
Crystal oscillator interface
Crystal input frequency range: 10MHz to 40MHz
Output skew: 80ps (maximum)
RMS phase jitter @ 25MHz, (100Hz - 1MHz):
0.26ps (typical) (V
DD
= V
DDO
= 2.5V)
Phase noise:
Offset
Noise Power
100Hz .............. -129.7 dBc/Hz
1kHz .............. -144.4 dBc/Hz
10kHz .............. -147.3 dBc/Hz
100kHz .............. -157.3 dBc/Hz
5V tolerant enable inputs
Synchronous output enables
Operating power supply modes:
Full 3.3V, 2.5V and 1.8V,
mixed 3.3V core/2.5V output operating supply,
mixed 3.3V core/1.8V output operating supply,
mixed 2.5V core/1.8V output operating supply
-40C to 85C ambient operating temperature
Lead-Free package fully RoHS compliant
HiPerClockSTM
ICS
ICS83905I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Pacakge
Top View
XTAL_OUT
ENABLE 2
GND
BCLK0
V
DD
o
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE 1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
DD
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
ENABLE 1
ENABLE 2
XTAL_IN
XTAL_OUT
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
2
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. O
UTPUT
E
NABLE
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
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.
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.
1
=
0
1
BCLK5
BCLK0:4
ENABLE2
ENABLE1
F
IGURE
1. E
NABLE
T
IMING
D
IAGRAM
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
3
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
16 Lead TSSOP package
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
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N
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5
A
m
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
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B
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4
A
m
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
4
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
4G. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40C
TO
85C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
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%
5
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3
.
3
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D
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V
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2
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D
D
%
5
V
3
.
3
=
3
.
0
-
8
.
0
V
V
D
D
%
5
V
5
.
2
=
3
.
0
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.
0
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8
.
1
=
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*
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3
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0
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O
N
;
%
5
V
3
.
3
=
6
.
2
V
V
O
D
D
I
;
%
5
V
5
.
2
=
H
O
A
m
1
-
=
2
V
V
O
D
D
1
E
T
O
N
;
%
5
V
5
.
2
=
8
.
1
V
V
O
D
D
1
E
T
O
N
;
V
2
.
0
V
8
.
1
=
V
O
D
D
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83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
5
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
6A. AC C
HARACTERISTICS
,
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DD
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83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
6
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
6D. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
6C. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
7
Integrated
Circuit
Systems, Inc.
ICS83905I
L
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S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
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T
ABLE
6E. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
6F. AC C
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,
V
DD
= 2.5V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
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83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
8
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
YPICAL
P
HASE
N
OISE
AT
25MH
Z
(2.5V C
ORE
/ 2.5V O
UTPUT
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.26ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Raw Phase Noise Data
T
YPICAL
P
HASE
N
OISE
AT
25MH
Z
(3.3V C
ORE
/ 3.3V O
UTPUT
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.13ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Raw Phase Noise Data
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
9
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
1.8V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.40.9V
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
SCOPE
Qx
LVCMOS
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDO
-1.25V5%
V
DD
1.25V5%
3.3V
CORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.165V5%
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5 C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
SCOPE
Qx
LVCMOS
0.9V0.1V
-0.9V 0.1V
SCOPE
Qx
LVCMOS
1.6V0.025%
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
V
DD
,
V
DDO
GND
V
DD
,
V
DDO
GND
V
DD
,
V
DDO
GND
GND
GND
GND
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
10
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
t
PW
BCLKx
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
S
KEW
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
11
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
C
RYSTAL
I
NPUT
I
NTERFACE
Figure 1A shows an example of ICS83905I crystal interface with
a parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal
with loading capacitance CL = 18pF, we suggest C1 = 15pF and
C2 = 15pF to start with. These values may be slightly fine tuned
further to optimize the frequency accuracy for different board lay-
outs. Slightly increasing the C1 and C2 values will slightly reduce
the frequency. Slightly decreasing the C1 and C2 values will slightly
increase the frequency. For the oscillator circuit below, R1 can
be used, but is not required. For new designs, it is recommended
that R1 not be used.
F
IGURE
1. C
RYSTAL
O
SCILLATOR
I
NTERFACE
C1
15p
R1 (optional)
0
X1
18pF Parallel Cry stal
C2
15p
XTAL_IN
XTAL_OUT
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
12
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
L
AYOUT
G
UIDELINE
Figure 2 shows an example of ICS83905I application schematic.
In this example, the device is operated at V
DD
= 3.3V and V
DDO
=
3.3V. The decoupling capacitors should be located as close as
possible to the power pins. The input is driven by an 18pF load
resonant quartz crystal. The tuning capacitors (C1, C2) are fairly
accurate, but minor adjustments might be required. For the
LVCMOS output drivers, two termination examples are shown
in the schematic. For additional termination, examples are shown
in the LVCMOS Termination Application Note.
F
IGURE
2. Schematic of Recommended Layout
VDD
R2
31
C6
.1uF
VDDO
ENABLE 2
R4
100
Zo = 50 Ohm
VDD = 3.3V
C2
15pf
VDD
C1
15pF
LVCMOS
ENABLE 1
CL = 18 pf
Optional Termination
R3
100
C4
.1uF
LVCMOS
Zo = 50 Ohm
VDDO
U1
ICS83905I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XTAL_OUT
ENABLE 2
GND
BCLK0
VDDO
BCLK1
GND
BCLK2
VDD
BCLK3
GND
BCLK4
VDDO
BCLK5
ENABLE 1
XTAL_IN
C3
10uF
VDDO = 3.3V
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
C5
.1uF
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
13
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83905I is: 339
Pin compatible to MPC905
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
14
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
Reference Document: JEDEC Publication 95, MO-153
L
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.
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A
5
0
.
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1
.
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0
.
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ABLE
8. P
ACKAGE
D
IMENSIONS
FOR
TSSOP
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
15
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
83905AGI
http://www.icst.com/products/hiperclocks.html
REV. B MAY 16, 2005
16
Integrated
Circuit
Systems, Inc.
ICS83905I
L
OW
S
KEW
, 1:6 C
RYSTAL
I
NTERFACE
-
TO
-
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
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