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Электронный компонент: 8430CY-01

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8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8430-01 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Fre-
quency Synthesizer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8430-01 has a select-
able TEST_CLK or crystal inputs. The VCO operates at a fre-
quency range of 250MHz to 500MHz. The VCO frequency is
programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
figuration logic. Frequency steps as small as 1MHz can be
achieved using a 16MHz crystal or TEST_CLK.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or
LVCMOS TEST_CLK
Output frequency range: 20.83MHz to 500MHz
Crystal input frequency range: 14MHz to 27MHz
VCO range: 250MHz to 500MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 6ps (maximum)
Cycle-to-cycle jitter: 30ps (maximum)
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
N 2
V
EE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
X
T
AL2
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OSC
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
N
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
16
PHASE DETECTOR
ICS8430-01
MR
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-01 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided
by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL
operates over a range of 250MHz to 500MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-01 support two input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hard-
wired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The
TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 250
M
500. The frequency out is
defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the TEST output as follows:
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N2
nP_LOAD
16
M
fVCO =
fxtal x
N
fout =
fVCO
=
16
M
fxtal x
N
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
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T
ABLE
2. P
IN
C
HARACTERISTICS
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8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
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8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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p
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5
1
A
m
NOTE 1: Outputs terminated with 50
to V
CCO
/2.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
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;
K
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1
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;
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HARACTERISTICS
, V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
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3
"
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ERIOD
J
ITTER
O
UTPUT
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
, V
CCA
, V
CCO
= 2V
C
YCLE
-
TO
-C
YCLE
J
ITTER
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
O
UTPUT
R
ISE
/F
ALL
T
IME
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
odc & t
P
ERIOD
V
EE
= -1.3V 0.165V
tsk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
nFOUTx
FOUTx
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
FOUTx
nFOUTx
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The ICS8430-01 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 24.
Figure 3A shows how to interface with a crystal.
Figures 3A, 3B, and 3C show various crystal parameters which
are recommended only as guidelines.
Figure 3A shows how to
interface a capacitor with a parallel resonant crystal.
Figure 3B
shows the capacitor value needed for the optimum ppm perfor-
F
IGURE
3B. Recommended tuning capacitance for various
parallel resonant crystals.
F
IGURE
3C. Recommended tuning capacitance for various
parallel resonant crystals.
14.318
15.000
16.667
24.000
19.440
20.000
0
10
20
30
40
50
60
14
15
16
17
18
19
20
21
22
23
24
25
Crystal Frequency (MHz)
S
e
r
i
es
C
apac
itor
, C
1
(
p
F
)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
60
Series Capacitor, C1 (pF)
F
r
equency A
ccur
a
cy (
ppm
)
19.44MHz
16MHz
15.00MHz
C
RYSTAL
I
NPUT
AND
O
SCILLATOR
I
NTERFACE
A
PPLICATION
I
NFORMATION
F
IGURE
3A. C
RYSTAL
I
NTERFACE
Optional
XTAL2
(Pin 25, LQFP)
XTAL1
(Pin 24, LQFP)
ICS8430-01
mance over various parallel resonant crystals.
Figure 3C shows
the recommended tuning capacitance for various parallel reso-
nant crystals.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
CCA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The schematic of the ICS8430-01 layout example used in
this layout guideline is shown in
Figure 5A. The ICS8430-01
recommended PCB board layout for this example is shown in
Figure 5B. This layout example is used as a general guideline.
L
AYOUT
G
UIDELINE
F
IGURE
5A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
XTAL_SEL
S_DATA
C11
0.1u
R3
50
IN+
C14
0.1u
Termination A
R7
10
R2
84
IN+
R2
50
TEST
MR
R3
125
TL1
Zo = 50 Ohm
Termination B
(Not shown in
the layout)
S_CLOCK
FO
U
T
N
C15
0.1u
FO
U
T
R1
50
VC
C
REF_IN
IN-
VCC
IN-
VC
C
R4
84
X1
TL2
Zo = 50 Ohm
R1
125
U1
8430-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
N2
VEE
TEST
VC
C
FO
U
T
1
nFO
U
T1
V
CCO
FO
U
T
0
nFO
U
T0
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
TEST_CLK
XTAL1
M4
M3
M2
M1
M0
VC
O
_
SEL
nP_LO
AD
XTAL2
C16
10u
S_LOAD
VCC0
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
Z
o
= 50
Z
o
= 50
The layout in the actual system will depend on the selected
component types, the density of the components, the density
of the traces, and the stack up of the P.C. board.
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
CCA
shares the same power supply with V
CC
, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
The traces with 50
transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS8430-01
TL1, TL2 are 50 Ohm traces and
equal length
C15
C16
VCC
TL
1
R4
VIA
R7
R1
GND
U1
TL1
R3
X1
Close to the input
pins of the
receiver
C14
PIN 1
T
L1N
VCCA
TL1N
R2
C11
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485.1mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power
_MAX
(3.465V, with all outputs switching) = 485.1mW + 60.4mW = 545.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.546W * 42.1C/W = 93C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
8. T
HERMAL
R
ESISTANCE
q
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
12
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
13
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8430-01 is: 4270
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
14
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
15
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
16
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
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