8432CY-11
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 15, 2002
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8432-11 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Frequency
Synthesizer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8432-11 has a selectable TEST_CLK
or crystal inputs. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL levels.
The VCO operates at a frequency range of 200MHz to 700MHz.
The VCO frequency is programmed in steps equal to the value
of the input reference or crystal frequency. Output frequencies
up to 700MHz for FOUT and 350MHz for FOUT/2 can be pro-
grammed using the serial or parallel interfaces to the configura-
tion logic. The low phase noise characteristics and the multiple
frequency outputs of the ICS8432-11 makes it an ideal clock
source for Fiber Channel 1 and 2, and Infiniband applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or
LVCMOS TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
Maximum FOUT frequency: 700MHz
Maximum FOUT/2 frequency: 350MHz
VCO range: 200MHz to 700 MHz
Parallel interface for programming counter and
VCO frequency multiplier and dividers
Cycle-to-cycle jitter: 25ps (maximum)
RMS period jitter: TBD
3.3V supply voltage
0C to 70C ambient operating temperature
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
HiPerClockSTM
,&6
OSC
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT
nFOUT
FOUT/2
nFOUT/2
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
N
2
MR
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
nc
V
EE
V
EE
nFOUT
FOUT
V
CCO
nFOUT/2
FOUT/2
V
CC
TEST
XT
AL2
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
ICS8432-11
8432CY-11
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 15, 2002
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the
phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over
a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-11 support two input modes and programmable M divider and N output divider.
The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel mode the
nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded
until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the
M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock are defined as 8
M
28. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the
S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output
divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the TEST output as follows:
fVCO = fxtal x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data
1
0
Output of M divider
1
1
CMOS Fout
FOUT = fVCO = fxtal x M
N
N
F
IGURE
1 - P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
Time
T1
T0
*NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N1
nP_LOAD
*NOTE: The NULL timing slot must be observed.
8432CY-11
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 15, 2002
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
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8432CY-11
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 15, 2002
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
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3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
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T
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3C. P
ROGRAMMABLE
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UTPUT
D
IVIDER
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2
8432CY-11
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 15, 2002
5
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
X
4.6V
Inputs, V
CC
-0.5V to V
CC
+ 0.5 V
Outputs, V
CCO
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
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CC
= V
CCA
= V
CCO
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A
= 0C
TO
70C
NOTE 1: Outputs terminated with 50
to V
CCO
/2. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
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