8432CY-111
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 3, 2001
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8432-111 is a general purpose, dual output
Differential-to-3.3V LVPECL High Frequency
Synthesizer and a member of the HiPerClockSTM
family of High Performance Clocks Solutions
from ICS. The ICS8432-111 has a selectable
differential CLK, nCLK pair or LVCMOS TEST_CLK. The
TEST_CLK input accepts LVCMOS or LVTTL input levels
and translates them to 3.3V LVPECL levels. The CLK, nCLK
pair can accept most standard differential input levels.The
VCO operates at a frequency range of 200MHz to 700MHz.
The VCO frequency is programmed in steps equal to the value
of the input differential or single ended reference frequency.
Output frequencies up to 700MHz for FOUT and 350MHz for
FOUT/2 can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics and the multiple frequency outputs of the
ICS8432-111 makes it an ideal clock source for Fiber Channel 1
and 2, and Infiniband applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable differential CLK, nCLK pair or LVCMOS TEST_CLK
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVHSTL, LVDS, SSTL, HCSL
TEST_CLK can accept the following input types:
LVCMOS or LVTTL
Maximum FOUT frequency up to 700MHz
Maximum FOUT/2 frequency up to 350MHz
14MHz to 25MHz differential input or TEST_CLK input
frequency
VCO range: 200MHz - 700MHz
Parallel or serial interface for programming counter and
VCO frequency multiplier and dividers
RMS period jitter: TBD
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
0C to 70C ambient operating temperature
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT
nFOUT
FOUT/2
nFOUT/2
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
N
2
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
nc
V
EE
V
EE
nFOUT
FOUT
V
CCO
nFOUT/2
FOUT/2
V
CC
TEST
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
ICS8432-111
nCLK
MR
HiPerClockSTM
,&6
8432CY-111
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 3, 2001
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Time
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for
different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-111 features a fully integrated PLL and therefore requires no external components for setting the loop band-
width. A differential clock input is used as the input to the ICS8432-111. This input is fed into the phase detector. A 25MHz
clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 200MHz to
700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50%
output duty cycle.
The programmable features of the ICS8432-111 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial.
Figure1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the input frequency and the loop divider is defined
as follows:
The M count and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 8
M 28. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when S_LOAD
transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to the ripple counter on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the
state of the TEST output as follows:
fVCO = f
IN
x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data
1
0
Output of M divider
1
1
CMOS Fout/2
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
fOUT = fVCO = f
IN
x M
N
N
*NOTE:
The NULL timing slot must be observed.
T1
T0
*
NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N1
nP_LOAD
8432CY-111
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 3, 2001
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
1
5
M
t
u
p
n
I
p
u
ll
u
P
n
o
i
t
s
i
s
n
a
r
t
H
G
I
H
-
o
t
-
W
O
L
n
o
d
e
h
c
t
a
l
a
t
a
D
.
s
t
u
p
n
i
r
e
d
i
v
i
d
/
r
e
t
n
u
o
c
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
D
A
O
L
_
P
n
f
o
,
4
,
3
,
2
,
9
2
,
8
2
2
3
,
1
3
,
0
3
,
8
M
,
7
M
,
6
M
,
1
M
,
0
M
4
M
,
3
M
,
2
M
t
u
p
n
I
n
w
o
d
ll
u
P
6
,
5
1
N
,
0
N
t
u
p
n
I
n
w
o
d
ll
u
P
n
o
i
t
c
n
u
F
C
3
e
l
b
a
T
n
i
d
e
n
i
f
e
d
s
a
e
u
l
a
v
r
e
d
i
v
i
d
t
u
p
t
u
o
s
e
n
i
m
r
e
t
e
D
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
l
b
a
T
7
c
n
d
e
s
u
n
U
.
t
c
e
n
n
o
c
o
N
6
1
,
8
V
E
E
r
e
w
o
P
.
d
n
u
o
r
g
o
t
t
c
e
n
n
o
C
.
s
n
i
p
y
l
p
p
u
s
e
v
i
t
a
g
e
N
9
T
S
E
T
t
u
p
t
u
O
.
n
o
i
t
a
r
e
p
o
f
o
e
d
o
m
l
a
i
r
e
s
e
h
t
n
i
E
V
I
T
C
A
s
i
h
c
i
h
w
t
u
p
t
u
o
t
s
e
T
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
S
O
M
C
V
L
.
e
d
o
m
l
e
ll
a
r
a
p
n
i
W
O
L
n
e
v
i
r
d
t
u
p
t
u
O
0
1
V
C
C
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
v
i
t
i
s
o
P
2
1
,
1
1
2
/
T
U
O
F
n
,
2
/
T
U
O
F
t
u
p
t
u
O
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
d
y
c
n
e
u
q
e
r
f
f
l
a
H
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
V
3
.
3
3
1
V
O
C
C
r
e
w
o
P
.
V
3
.
3
o
t
t
c
e
n
n
o
C
.
n
i
p
y
l
p
p
u
s
t
u
p
t
u
O
5
1
,
4
1
T
U
O
F
n
,
T
U
O
F
t
u
p
t
u
O
.
r
e
z
i
s
e
h
t
n
y
s
e
h
t
r
o
f
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
V
3
.
3
7
1
R
M
t
u
p
n
I
n
w
o
d
ll
u
P
,
M
d
e
d
a
o
l
t
c
e
f
f
e
t
o
n
s
e
o
d
t
u
b
,
W
O
L
s
t
u
p
t
u
o
s
e
c
r
o
F
.
t
e
s
e
r
r
e
t
s
a
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
e
u
l
a
v
T
d
n
a
,
N
8
1
K
C
O
L
C
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
o
t
n
i
t
u
p
n
i
A
T
A
D
_
S
t
a
t
n
e
s
e
r
p
a
t
a
d
l
a
i
r
e
s
n
i
s
k
c
o
l
C
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
e
h
t
n
o
9
1
A
T
A
D
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
f
o
e
g
d
e
g
n
i
s
i
r
e
h
t
n
o
d
e
l
p
m
a
s
a
t
a
D
.
t
u
p
n
i
l
a
i
r
e
s
r
e
t
s
i
g
e
r
t
f
i
h
S
.
K
C
O
L
C
_
S
0
2
D
A
O
L
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
r
e
t
n
u
o
c
e
l
p
p
i
r
e
h
t
o
t
n
i
r
e
t
s
i
g
e
r
t
f
i
h
s
m
o
r
f
a
t
a
d
f
o
n
o
i
t
i
s
n
a
r
t
s
l
o
r
t
n
o
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
1
2
V
A
C
C
r
e
w
o
P
.
V
3
.
3
o
t
t
c
e
n
n
o
C
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
2
2
L
E
S
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
L
L
P
e
h
t
s
a
t
u
p
n
i
t
s
e
t
r
o
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
n
e
e
w
t
e
b
s
t
c
e
l
e
S
,
K
L
C
s
t
c
e
l
e
S
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
c
r
u
o
s
e
c
n
e
r
e
f
e
r
.
W
O
L
n
e
h
w
K
L
C
_
T
S
E
T
s
t
c
e
l
e
S
.
H
G
I
H
n
e
h
w
s
t
u
p
n
i
K
L
C
n
3
2
K
L
C
_
T
S
E
T
t
u
p
n
I
n
w
o
d
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
k
c
o
l
c
t
s
e
T
4
2
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
i
-
n
o
N
5
2
K
L
C
n
t
u
p
n
I
p
u
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
6
2
D
A
O
L
_
P
n
t
u
p
n
I
n
w
o
d
ll
u
P
s
i
0
M
:
8
M
t
a
t
n
e
s
e
r
p
a
t
a
d
n
e
h
w
s
e
n
i
m
r
e
t
e
D
.
t
u
p
n
i
d
a
o
l
l
e
ll
a
r
a
P
s
t
e
s
0
N
:
1
N
t
a
t
n
e
s
e
r
p
a
t
a
d
n
e
h
w
d
n
a
,
r
e
t
n
u
o
c
e
l
p
p
i
r
o
t
n
i
d
e
d
a
o
l
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
u
l
a
v
r
e
d
i
v
i
d
t
u
p
t
u
o
e
h
t
7
2
L
E
S
_
O
C
V
t
u
p
n
I
p
u
ll
u
P
.
e
d
o
m
s
s
a
p
y
b
r
o
L
L
P
n
i
s
i
r
e
z
i
s
e
h
t
n
y
s
r
e
h
t
e
h
w
s
e
n
i
m
r
e
t
e
D
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
s
r
e
f
e
r
T
ABLE
2. P
IN
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
K
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
K
8432CY-111
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 3, 2001
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
s
t
u
p
n
I
s
n
o
i
t
i
d
n
o
C
R
M
D
A
O
L
_
P
n
M
N
D
A
O
L
_
S
K
C
O
L
C
_
S
A
T
A
D
_
S
H
X
X
X
X
X
X
.
t
e
s
e
r
s
r
e
t
n
u
o
c
N
d
n
a
M
.
t
e
s
e
R
L
L
a
t
a
D
a
t
a
D
X
X
X
e
l
p
p
i
r
e
h
t
o
t
y
l
t
c
e
r
i
d
d
e
s
s
a
p
s
t
u
p
n
i
N
d
n
a
M
n
o
a
t
a
D
.
W
O
L
d
e
c
r
o
f
t
u
p
t
u
o
T
S
E
T
.
r
e
d
i
v
i
d
t
u
p
t
u
o
d
n
a
r
e
t
n
u
o
c
L
a
t
a
D
a
t
a
D
L
X
X
d
e
d
a
o
l
s
n
i
a
m
e
r
d
n
a
s
r
e
t
s
i
g
e
r
t
u
p
n
i
o
t
n
i
d
e
h
c
t
a
l
s
i
a
t
a
D
.
s
r
u
c
c
o
t
n
e
v
e
l
a
i
r
e
s
a
li
t
n
u
r
o
n
o
i
t
i
s
n
a
r
t
W
O
L
t
x
e
n
li
t
n
u
L
H
X
X
L
a
t
a
D
n
o
a
t
a
d
h
t
i
w
d
e
d
a
o
l
s
i
r
e
t
s
i
g
e
r
t
f
i
h
S
.
e
d
o
m
t
u
p
n
i
l
a
i
r
e
S
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
h
c
a
e
n
o
A
T
A
D
_
S
L
H
X
X
L
a
t
a
D
e
l
p
p
i
r
e
h
t
o
t
d
e
s
s
a
p
e
r
a
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
f
o
s
t
n
e
t
n
o
C
.
r
e
d
i
v
i
d
t
u
p
t
u
o
d
n
a
r
e
t
n
u
o
c
L
H
X
X
L
a
t
a
D
.
d
e
h
c
t
a
l
e
r
a
s
e
u
l
a
v
r
e
d
i
v
i
d
t
u
p
t
u
o
d
n
a
r
e
t
n
u
o
c
e
l
p
p
i
R
L
H
X
X
L
X
X
.
s
r
e
t
s
i
g
e
r
t
f
i
h
s
t
c
e
f
f
a
t
o
n
o
d
t
u
p
n
i
l
a
i
r
e
s
r
o
l
e
ll
a
r
a
P
L
H
X
X
H
a
t
a
D
s
i
t
i
s
a
r
e
t
n
u
o
c
e
l
p
p
i
r
o
t
y
l
t
c
e
r
i
d
d
e
s
s
a
p
A
T
A
D
_
S
.
d
e
k
c
o
l
c
W
O
L
=
L
:
E
T
O
N
H
G
I
H
=
H
e
r
a
c
t
'
n
o
D
=
X
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
i
s
i
R
=
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
il
l
a
F
=
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
y
c
n
e
u
q
e
r
F
O
C
V
)
z
H
M
(
t
n
u
o
C
M
6
5
2
8
2
1
4
6
2
3
6
1
8
4
2
1
8
M
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
M
0
0
2
8
0
0
0
0
0
1
0
0
0
5
2
2
9
0
0
0
0
0
1
0
0
1
0
5
2
0
1
0
0
0
0
0
1
0
1
0
5
7
2
1
1
0
0
0
0
0
1
0
1
1
0
5
6
6
2
0
0
0
0
1
1
0
1
0
5
7
6
7
2
0
0
0
0
1
1
0
1
1
0
0
7
8
2
0
0
0
0
1
1
1
0
0
y
c
n
e
u
q
e
r
f
t
u
p
n
i
K
L
C
_
T
S
E
T
r
o
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
o
t
d
n
o
p
s
e
r
r
o
c
s
e
i
c
n
e
u
q
e
r
f
g
n
i
t
l
u
s
e
r
e
h
t
d
n
a
s
e
u
l
a
v
t
n
u
o
c
M
e
s
e
h
T
:
1
E
T
O
N
.
z
H
M
5
2
f
o
s
t
u
p
n
I
e
u
l
a
V
r
e
d
i
v
i
D
N
)
z
H
M
(
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
T
U
O
F
2
/
T
U
O
F
1
N
0
N
m
u
m
i
n
i
M
m
u
m
i
x
a
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
0
0
1
0
0
2
0
0
7
5
2
1
0
5
3
0
1
2
0
0
1
0
5
3
5
.
2
6
5
7
1
1
0
4
0
5
5
7
1
5
2
.
1
3
5
.
7
8
1
1
8
5
2
5
.
7
8
5
2
6
.
5
1
5
7
.
3
4
8432CY-111
www.icst.com/products/hiperclocks.html
REV. D DECEMBER 3, 2001
5
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these condition or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
, V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
e
v
i
t
i
s
o
P
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
C
C
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
E
E
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
1
1
A
m
I
A
C
C
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
5
1
A
m
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
, V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
t
u
p
n
I
e
g
a
t
l
o
V
h
g
i
H
,
L
E
S
_
K
L
C
,
L
E
S
_
O
C
V
,
K
C
O
L
C
_
S
,
A
T
A
D
_
S
,
D
A
O
L
_
S
R
M
,
8
M
:
0
M
,
1
N
:
0
N
,
D
A
O
L
_
P
n
2
V
C
C
3
.
0
+
V
K
L
C
_
T
S
E
T
2
V
C
C
3
.
0
+
V
V
L
I
t
u
p
n
I
e
g
a
t
l
o
V
w
o
L
,
L
E
S
_
K
L
C
,
L
E
S
_
O
C
V
,
K
C
O
L
C
_
S
,
A
T
A
D
_
S
,
D
A
O
L
_
S
R
M
,
8
M
:
0
M
,
1
N
:
0
N
,
D
A
O
L
_
P
n
3
.
0
-
8
.
0
V
K
L
C
_
T
S
E
T
3
.
1
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
,
1
N
,
0
N
,
8
M
-
6
M
,
4
M
-
0
M
,
D
A
O
L
_
S
,
A
T
A
D
_
S
,
K
C
O
L
C
_
S
R
M
,
D
A
O
L
_
P
n
,
K
L
C
_
T
S
E
T
*V
C
C x
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
L
E
S
_
O
C
V
,
L
E
S
_
K
L
C
,
5
M
*V
C
C x
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
,
1
N
,
0
N
,
8
M
-
6
M
,
4
M
-
0
M
,
D
A
O
L
_
S
,
A
T
A
D
_
S
,
K
C
O
L
C
_
S
R
M
,
D
A
O
L
_
P
n
,
K
L
C
_
T
S
E
T
*V
C
C x
,
V
5
6
4
.
3
=
V
N
I
V
0
=
5
-
A
L
E
S
_
O
C
V
,
L
E
S
_
K
L
C
,
5
M
*V
C
C x
,
V
5
6
4
.
3
=
V
N
I
V
0
=
0
5
1
-
A
V
H
O
t
u
p
t
u
O
e
g
a
t
l
o
V
h
g
i
H
1
E
T
O
N
;
T
S
E
T
6
.
2
V
V
L
O
t
u
p
t
u
O
e
g
a
t
l
o
V
w
o
L
1
E
T
O
N
;
T
S
E
T
5
.
0
V
NOTE 1: Outputs terminated with 50
to V
CCO
/2. See page 8, Figure 2, 3.3V Output Load Test Circuit.
*NOTE: V
CCx
denotes V
CC
, V
CCA
, and V
CCO
.
PDF 
ZIP