Integrated
Circuit
Systems, Inc.
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
8521BY
www.icst.com/products/hiperclocks.html
REV. C JANUARY 2, 2003
1
G
ENERAL
D
ESCRIPTION
The ICS8521 is a low skew, 1-to-9 Differential-
to-LVHSTL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8521 has two select-
able clock inputs. The CLK, nCLK pair can ac-
cept most standard differential input levels. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today's
most advanced applications, such as IA64 and static RAMs.
HiPerClockSTM
,&6
F
EATURES
9 LVHSTL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.8ns (maximum)
V
OH
= 1.4V (maximum)
3.3V core, 1.8V output operating supply voltages
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
9 1 0 1 1 1 2 1 3 1 4 1 5 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
DDO
ICS8521
V
DDO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DDO
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
CLK_EN
32-Lead LQFP
7mm x 7mm x 1.4mm Package Body
Y Package
Top View
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
D
Q
LE
CLK_EN
CLK_SEL
0
1
Integrated
Circuit
Systems, Inc.
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
8521BY
www.icst.com/products/hiperclocks.html
REV. C JANUARY 2, 2003
4
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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=
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=
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=
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3
=
5
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n
V
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V
,
V
0
=
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5
6
4
.
3
=
0
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1
-
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V
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V
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c
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p
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g
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F
:
1
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T
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N
D
D
.
V
3
.
0
+
V
s
a
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n
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f
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m
o
C
:
2
E
T
O
N
H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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