ICS8523 Final Data Sheet
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
G
ENERAL
D
ESCRIPTION
The ICS8523 is a low skew, high perfor-
mance 1-to-4 Differential-to-LVHSTL fanout buffer
and a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
F
EATURES
4 differential LVHSTL compatible outputs
Selectable diffferential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 650MHz
Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation delay: 1.6ns (maximum)
3.3V core, 1.8V output operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
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NPUT
F
UNCTION
T
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1. CLK_EN T
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CLK, PCLK
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8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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m
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C
:
2
E
T
O
N
H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
X
4.6V
Inputs, V
DD
-0.5V to V
DD
+ 0.5 V
Outputs, V
DDO
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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%
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8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ3
Q0:Q3
t
PD
nCLK,
nPCLK
CLK,
PCLK
nQ0:nQ3
Q0:Q3
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
3.3V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
odc & t
P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
tsk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
nCLK, nPCLK
CLK, PCLK
GND
V
DD
SCOPE
LVHSTL
Qx
nQx
3.3V5%
V
DDO
V
DD
GND = 0V
1.8V0.2V
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4 to 7 show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
F
IGURE
4. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 4, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
S
CHEMATIC
E
XAMPLE
Figure 3 shows a schematic example of the ICS8523. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
1.8V
LVHSTL Driver
Zo = 50
Zo = 50
C2
0.1u
R5
50
R6
50
R10
50
1.8V
R11
1K
R3
50
Zo = 50 Ohm
U3
8523
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
NC
NC
VDD
nQ3
Q3
VDDO
nQ2
Q2
nQ1
Q0
nQ0
VDDO
Q1
Zo = 50
+
-
Zo = 50 Ohm
Zo = 50
R4
50
R12
1K
R1
50
1.8V
1.8V
+
-
R7
50
R2
50
3.3V
C3
0.1u
R9
50
+
-
Zo = 50
R8
50
+
-
Zo = 50
3.3V
Zo = 50
Zo = 50
C1
0.1u
F
IGURE
3. ICS8523 LVHSTL B
UFFER
S
CHEMATIC
E
XAMPLE
near the power pin. For ICS8523, the unused clock outputs can
be left floating.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
IGURE
6. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
5. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
7. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
PCLK/nPCLK C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differ-
ential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 8 to 11 show interface examples for
the HiPerClockS PCLK/nPCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination rec-
ommendation. Please consult with the vendor of the driver compo-
nent to confirm the driver termination requirements.
F
IGURE
8. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
CML D
RIVER
F
IGURE
9. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
AN
SSTL
IN
D
RIVER
F
IGURE
10. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
11. H
I
P
ER
C
LOCK
S PCLK/
N
PCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 50mA = 173.3mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.8mW = 131.2mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.3mW + 131.2mW = 305mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.305W * 66.6C/W = 90.3C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE
q
JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 12.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DDO_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DDO_MAX
- V
OL_MAX
)
Pd_H = (1V/50
) * (2V - 1V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
12. LVHSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8523 is: 472
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
14
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-153
L
O
B
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Y
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8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
15
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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t
C
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8523BG
www.icst.com/products/hiperclocks.html
REV. C OCTOBER 25, 2002
16
Integrated
Circuit
Systems, Inc.
ICS8523
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
T
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Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- CLK_EN Timing Diagram
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- LVHSTL DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V/1.8V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input
- Schematic Example
- Differential Clock Input Interface
- HiPerClockS CLK/nCLK Input Driven by ICS HiPerClockS LVHST Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver Diagram
- HiPerClockS CLK/nCLK Input Driven by 3.3V LVPECL Driver with AC Couple Diagram
- PCLK/nPCLK Clock Input Interface
- HiPerClockS PCLK/nPCLK Input Driven by a CML Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by an SSTL in Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver Diagram
- HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Diagram
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVHSTL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
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