Integrated
Circuit
Systems, Inc.
8702BY
www.icst.com/products/hiperclocks.com
REV. C NOVEMBER 28, 2001
1
ICS8702
L
OW
S
KEW
,
1,
2
D
IFFERENTIAL
-
TO
-LVCMOS C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8702 is a low skew,
1,
2 Differential-to-
LVCMOS Clock Generator and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8702 is designed to
translate any differential signal levels to LVCMOS
levels. True or inverting, single-ended to LVCMOS translation
can be achieved with a resistor bias on the nCLK or CLK in-
puts, respectively. The effective fanout can be increased from
20 to 40 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the
1,
2 or a
combination of
1 and
2 modes. The bank enable inputs,
BANK_EN0:1, supports enabling and disabling each bank of
outputs individually. The master reset input, nMR/OE, resets
the internal frequency dividers and also controls the enabling
and disabling of all outputs simultaneously.
The ICS8702 is characterized at 3.3V and mixed 3.3V input sup-
ply, and 2.5V output supply operating modes. Guaranteed bank,
output, multiple frequency and part-to-part skew characteristics
make the ICS8702 ideal for those clock distribution applications
demanding well defined performance and repeatability.
F
EATURES
20 LVCMOS outputs, 7
typical output impedance
1 differential clock input pair
CLK, nCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency up to 250MHz
Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS levels without external bias networks
Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
Output skew: 200ps (maximum)
Bank skew: 150ps (maximum)
Part-to-part skew: 650ps (maximum)
Multiple frequency skew: 250ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
0C to 70C ambient operating temperature
Other divide values available on request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
CLK
nCLK
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
V
DDO
QC4
QD0
V
DDO
QD1
GND
QD2
GND
QD3
V
DDO
QD4
QB1
V
DDO
QB0
QA4
V
DDO
QA3
GND
QA2
GND
QA1
V
DDO
QA0
DIV_SELA
DIV_SELB
CLK
nCLK
V
DD
BANK_EN0
GND
BANK_EN1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8702
HiPerClockSTM
,&6
1
0
1
0
1
0
1
0
Bank Enable
Logic
1
2