8745AM-21
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8745-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8745-21 is a highly versatile 1:1 LVDS
c l o c k g e n e r a t o r a n d a m e m b e r o f t h e
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8745-21 has a fully
integrated PLL and can be configured as zero
delay buffer, multiplier or divider, and has an output fre-
quency range of 31.25MHz to 700MHz. The Reference
Divider, Feedback Divider and Output Divider are each
programmable, thereby allowing for the following output-
to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.
The external feedback allows the device to achieve "zero
delay" between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal
output dividers.
F
EATURES
1 differential LVDS output pair designed to meet
or exceed the requirements of ANSI TIA/EIA-644
1 differential feedback output pair
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 25ps (maximum)
Static phase offset: 50ps 150ps
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8745-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
V
DDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q
nQ
QFB
nQFB
0
1
1, 2, 4, 8,
16, 32, 64
8745AM-21
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8745-21
D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
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b
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=
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-
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,
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3
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T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
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1
L
E
S
,
0
L
E
S
,
R
M
3
L
E
S
,
2
L
E
S
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
L
E
S
_
L
L
P
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
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t
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p
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I
,
1
L
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S
,
0
L
E
S
,
R
M
3
L
E
S
,
2
L
E
S
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
L
E
S
_
L
L
P
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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