Integrated
Circuit
Systems, Inc.
General Description
Features
AV9155C
Block Diagram
AV9155C Rev F 12/13/00
Low Cost 20-Pin Frequency Generator
The AV9155C is a low cost frequency generator designed
specifically for desktop and notebook PC applications with
either 3.3V or 5.0V power supply voltage. Its CPU clocks
provide all necessary CPU frequencies for 286, 386 and 486
systems, including support for the latest speeds of processors.
The device uses a 14.318 MHz crystal to generate the CPU
and all peripheral clocks for integrated desktop motherboards.
The dual 14.318 MHz clock outputs allows one output for the
system and one to be the input to an ICS graphics frequency
generator such as the AV9194.
The CPU clock offers the unique feature of smooth, glitch-
free transitions from one frequency to the next, making this
ideal device to use whenever slowing the CPU speed. The
AV9155C makes a gradual transition between frequencies, so
that it obeys the Intel cycle-to-cycle timing specification for
486 systems. The simultaneous 2X and 1X CPU clocks offer
controlled skew to within 1.5ns (max) of each other.
ICS offers several versions of the AV9155C. The different
devices are shown below:
Compatible with 286, 386, and 486 CPUs
Supports turbo modes
Generates communications clock, keyboard clock,
floppy disk clock, system reference clock, bus clock
and CPU clock
Output enable tristates outputs
Up to 100 MHz at 5V or 3.3V
20-pin DIP or SOIC
All loop filter components internal
Skew-controlled 2X and 1X CPU clocks
Power-down option
ICS has been shipping motherboard frequency generators
since April 1990, and is the leader in the area of multiple
output clocks on a single chip. The AV9155C is a third
generation device, and uses ICS's patented analog CMOS
phase-locked loop technology for low phase jitter. ICS offers
a broad family of frequency generators for motherboards,
graphics and other applications, including cost-effective
versions with only one or two output clocks. Consult ICS for
all of your clock generation needs.
Pentium is a trademark of Intel Corporation.
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AV9155C
Pin Configuration
20-Pin DIP or SOIC
20-Pin DIP or SOIC
Pin Descriptions for AV9155C-01, -02
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AV9155C
Functionality
- AV9155C-01
(Using 14.318 MHz input. All frequencies in MHz.)
CLOCK#2 CPU and 2XCPU
*V
DD
minimum 3.15V.
PERIPHERAL CLOCKS
REFERENCE CLOCKS
Functionality - AV9155C-02
(Using 14.318 MHz input. All frequencies in MHz.)
CLOCK#2 CPU and 2XCPU
* V
DD
minimum 3.15V
PERIPHERAL CLOCKS
REFERENCE CLOCKS
Frequency Transitions
A key feature of the AV9155C is its ability to provide smooth,
glitch-free frequency transitions on the CPU and 2XCPU
clocks when the frequency select pins are changed. These
frequency transitions do not violate the Intel 486 specification
of less than 0.1% frequency change per clock period.
Using an Input Clock as Reference
The AV9155C is designed to accept a 14.318 MHz crystal as
the input reference. With some external changes, it is possible
to use a crystal oscillator or clock input. Please see application
note AN04 for details on driving the AV9155C with a clock.
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AV9155C
Pin Configuration
Pin Descriptions for AV9155C-23, -36
20-Pin DIP or SOIC
20-Pin DIP or SOIC
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AV9155C
CLOCK#2 CPU and 2XCPU
*V
DD
minimum 3.15V
PERIPHERAL CLOCKS
REFERENCE CLOCKS
CLOCK#2 CPU and 2XCPU
*V
DD
minimum 3.15V
PERIPHERAL CLOCKS
REFERENCE CLOCKS
K
L
C
M
M
O
C
)
1
n
i
P
(
n
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P
(
K
L
C
S
U
B
)
6
K
L
C
D
F
)
7
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(
K
L
C
B
K
)
8
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P
(
3
4
8
.
1
6
1
4
2
2
1
K
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C
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)
1
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(
n
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P
(
K
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C
S
U
B
)
6
K
L
C
D
F
)
7
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(
K
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C
B
K
)
8
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0
4
5
1
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2
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1
K
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F
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3
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2
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4
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8
1
3
.
4
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8
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3
.
4
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K
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3
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2
K
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4
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3
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4
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8
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4
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F
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1
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2
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7
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1
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8
6
1
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4
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6
6
.
6
6
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0
8
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0
0
1
4
8
0
3
0
2
5
2
3
3
.
3
3
*
0
4
*
0
5
Functionality
- AV9155C-23
(Using 14.318 MHz input. All frequencies in MHz.)
Functionality
- AV9155C-36
(Using 14.318 MHz input. All frequencies in MHz.)
2
S
F
)
1
1
n
i
P
(
1
S
F
)
9
1
n
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P
(
0
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0
2
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U
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2
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5
7
2
3
0
6
0
4
0
5
6
6
.
6
6
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0
8
2
5
*
5
.
7
3
6
1
0
3
0
2
5
2
3
3
.
3
3
*
0
4
6
2
6
AV9155C
Electrical Characteristics at 5V
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Operating temperature under bias. . . . . . . . . . . . . . . . 0C to +70C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
V
DD
= 4.0 to 5.5V (5V +10%/-20%); T
A=0
C to 70C unless otherwise stated
Notes:
1 Parameter is guaranteed by design and characterization, not subject to production testing.
s
c
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0
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2
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1
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3
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5
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0
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3
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0
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2
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0
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2
=
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4
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3
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K
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#
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0
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1
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1
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2
1
0
5
3
0
0
7
m
h
o
k
7
AV9155C
Electrical Characteristics at 5V
V
DD
= 4.0 to 5.5V (5V +10%/-20%); T
A=0
C to 70C unless otherwise stated
Notes:
1 Parameter is guaranteed by design and characterization, not subject to production testing.
s
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8
AV9155C
Electrical Characteristics at 3.3V
V
DD
=3.0V to 3.7V, T
A=0
C to 70C unless otherwise stated
Notes:
1 Parameter is guaranteed by design and characterization, not subject to production testing.
s
c
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w
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D
V
3
.
3
=
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-
V
2
.
0
D
D
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3
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.
0
D
D
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V
#
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3
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3
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2
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V
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=
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1
1
5
2
A
t
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r
r
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h
g
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5
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5
A
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w
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t
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D
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AV9155C
Electrical Characteristics at 3.3V
V
DD
= +3.3V10%, T
A
=0C to 70C unless otherwise stated
Notes:
1 Parameter is guaranteed by design and characterization, not subject to production testing.
2 Output frequencies on 2XCPU of 80 or 100 MHz require minimum V
DD of 3.15V (3.3 -5%).
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10
AV9155C
AV9155C-01 and AV9155C-02
CLOCK#2 CPU and 2XCPU
PERIPHERAL CLOCKS
Actual Output Frequencies
(Using 14.318 MHz input. All frequencies in MHz.)
AV9155C-23
CPU CLOCK
PERIPHERAL CLOCKS
AV9155C-36
CPU CLOCK
PERIPHERAL CLOCKS
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11
AV9155C
Notes:
1. ICS recommends the use of an isolated ground plane for the AV9155C. All grounds shown on this drawing should be
connected to this ground plane. This ground plane should be connected to the system ground plane at a single point. Please
refer to AV9155C Board Layout Diagram.
2. A single power supply connection for all VDD lines at the 2.2F decoupling capacitor is recommended to reduce interaction
of analog and digital circuits. The 0.1F decoupling capacitors should be located as close to each VDD pin as possible.
3. A 33
series termination resistor should be used on any clock output which drives more than one load or drives a long trace
(more than about two inches), especially when using high frequencies (>50 MHz). This termination resistor is put in series
with the clock output line close to the clock output. It helps improve jitter performance and reduce EMI by damping standing
waves caused by impedance mismatches in the output clock circuit trace.
4. The ferrite bead does not enhance the performance of the AV9155C, but will reduce EMI radiation from the VDD line.
AV9155C Recommended External Circuit
12
AV9155C
AV9155C Recommended Board Layout
This is the recommended layout for the AV9155C to maximize clock performance. Shown are the power and ground
connections, the ground plane, and the input/output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise
from propagating through the device. When compared to using the system ground and power planes, this technique will
minimize output clock jitter. The isolated ground plane should be connected to the system ground plane at one point, near the
2.2F decoupling cap. For lowest jitter performance, this isolated ground plane should be kept away from clock output pins
and traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap
between the isolated ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line optional,
but will help reduce EMI.
The traces to distribute the output clocks should be over a system ground or power supply plane. The trace width should be about
two times the thickness of the PC board between the trace and the underlying plane. These guidelines help minimize clock jitter
and EMI radiation. The traces to distribute power should be as wide as possible.
13
AV9155C
Ordering Information
Example:
20-Pin DIP Package
AV9155C-02CN20,
AV9155C-23CN20, AV9155C-36CN20
Notes:
Tape and reel packaging should be ordered with the suffix T&R. For instance, if the -01 in DIP and tape & reel is required,
order the part as AV9155C-01CN20T&R.
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3" SOIC or .6" DIP; None=Standard Width
Package Type
N=DIP (Plastic#) T&R=Tape and Reel
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
14
AV9155C
Ordering Information
AV9155C-01CW20, AV9155C-02CM20,
AV9155C-23CM20, AV9155C-36CM20
T
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ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3" SOIC or .6" DIP; None=Standard Width
Package Type
W=SOIC
T&R=Tape and Reel
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
Example:
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