ICS348-22
MDS 348-22 A
1
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
Quad PLL Field Programmable VersaClock Synthesizer
PRELIMINARY INFORMATION
Description
The ICS348-22 field programmable clock synthesizer
generates up to 9 high-quality, high-frequency clock
outputs including multiple reference clocks from a low
frequency crystal or clock input. The ICS348-22 has
four independent on-chip PLLs and is designed to
replace crystals and crystal oscillators in most
electronic systems.
Using ICS' VersaClock
TM
software to configure PLLs
and outputs, the ICS348-22 contains a One-Time
Programmable (OTP) ROM to allow field
programmability. Programming features include eight
selectable configuration registers, up to two sets of four
low-skew outputs.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
Features
Packaged as 20-pin SSOP (QSOP)
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 189 MHz at 3.3 V
Input crystal frequency of 25 MHz
Up to nine reference outputs
Up to two sets of four low-skew outputs
Operating voltages of 3.3 V
Advanced, low power CMOS process
Available in Pb (lead) free packaging
Block Diagram
Crystal
Oscillator
PLL1
GND
2
3
VDD
PDTS
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
S2:S0
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
3
OTP
ROM
with PLL
Values
PLL4
X2
25 MHz
crystal input
External capacitors are
required with a crystal input.
X1
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
2
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
Pin Assignment
Output Configuration Table
16
1
15
2
14
X1
X2
3
13
S0
4
12
S1
VDD
5
11
CLK9
6
PDTS
7
VDD
8
GND
S2
VDD
GND
CLK1
CLK5
CLK2
CLK6
9
10
CLK3
CLK7
CLK4
CLK8
20
19
18
17
20-pin (150 mil) SSOP (QSOP)
S2 S1 S0
Outputs
0
0
0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
0
0
1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
0
1
0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
0
1
1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1
0
0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1
0
1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1
1
0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1
1
1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=OFF, CLK8=189 MHz, CLK9=127 MHz
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
3
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
XI
Crystal Input. Connect this pin to a 25 MHz crystal.
2
S0
Input
Select pin 0. Internal pull-up resistor.
3
S1
Input
Select pin 1. Internal pull-up resistor.
4
CLK9
Output
127 MHz output clock. Weak internal pull-down when tri-state.
5
VDD
Power
Connect to +3.3 V.
6
GND
Power
Connect to ground.
7
CLK1
Output
127 MHz output clock. Weak internal pull-down when tri-state.
8
CLK2
Output
127 MHz output clock. Weak internal pull-down when tri-state.
9
CLK3
Output
127 MHz output clock. Weak internal pull-down when tri-state.
10
CLK4
Output
127 MHz output clock. Weak internal pull-down when tri-state.
11
CLK8
Output
189 MHz output clock. Weak internal pull-down when tri-state.
12
CLK7
Output
187 MHz output clock. Weak internal pull-down when tri-state.
13
CLK6
Output
187 MHz output clock. Weak internal pull-down when tri-state.
14
CLK5
Output
127 MHz output clock. Weak internal pull-down when tri-state.
15
GND
Power
Connect to ground.
16
VDD
Power
Connect to +3.3 V.
17
S2
Input
Select pin 2. Internal pull-up resistor.
18
PDTS
Input
Power down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
19
VDD
Power
Connect to +3.3 V.
20
X2
XO
Crystal Output. Connect this pin to a fundamental crystal. Float for clock input.
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
4
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS348-22 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination
resistor, if needed, should be placed close to the clock
output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers
ICS348 Configuration Capabilities
The architecture of the ICS348-22 allows the user to
easily configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS348-22 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user's target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
OutputFreq
REFFreq
OutputDivide
-------------------------------------- M
N
-----
=
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
5
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS348-22. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Parameter
Condition
Min.
Typ.
Max.
Units
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Storage Temperature
-65
150
C
Soldering Temperature
Max 10 seconds
260
C
Junction Temperature
125
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
Power Supply Ramp Time
4
ms
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
6
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C
Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
3.45
V
Operating Supply Current
Input High Voltage
IDD
Configuration Dependent
- See VersaClock
TM
Estimates
mA
Nine 33.3333 MHz outs,
PDTS = 1, no load, Note
1
23
mA
PDTS = 0, no load
20
A
Input High Voltage
V
IH
S2:S0
2
V
Input Low Voltage
V
IL
S2:S0
0.4
V
Input High Voltage, PDTS
V
IH
VDD-0.5
V
Input Low Voltage, PDTS
V
IL
0.4
V
Input High Voltage
V
IH
ICLK
VDD/2+1
V
Input Low Voltage
V
IL
ICLK
VDD/2-1
V
Output High Voltage
(CMOS High)
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 12 mA
0.4
V
Short Circuit Current
I
OS
70
mA
Nominal Output
Impedance
Z
O
20
Internal Pull-up Resistor
R
PUS
S2:S0, PDTS
250
k
Internal Pull-down
Resistor
R
PD
CLK outputs
525
k
Input Capacitance
C
IN
Inputs
4
pF
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
7
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS
transition high on select address change.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
Fundamental Crystal
25
MHz
Output Frequency
VDD=3.3 V
0.25
189
MHz
Output Rise Time
t
OR
20% to 80%, Note 1
1
ns
Output Fall Time
t
OF
80% to 20%, Note 1
1
ns
Duty Cycle
Note 2
40
49-51
60
%
Power-up time
PLL lock-time from
power-up, Note 3
3
10
ms
PDTS goes high until
stable CLK output, Note 3
0.2
2
ms
One Sigma Clock Period Jitter
Configuration Dependent
50
ps
Maximum Absolute Jitter
t
ja
Deviation from Mean.
Configuration Dependent
+200
ps
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
135
C/W
JA
1 m/s air flow
93
C/W
JA
3 m/s air flow
78
C/W
Thermal Resistance Junction to Case
JC
60
C/W
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348-22 A
8
Revision 120704
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS348-22
PRELIMINARY INFORMATION
Package Outline and Package Dimensions
(20-pin SSOP, 150 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
"LF" denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS348R-22
ICS348R-22
Tubes
20-pin SSOP
0 to +70
C
ICS348R-22T
ICS348R-22
Tape and Reel
20-pin SSOP
0 to +70
C
ICS348R-22LF
ICS348R22LF
Tubes
20-pin SSOP
0 to +70
C
ICS348R-22LFT
ICS348R22LF
Tape and Reel
20-pin SSOP
0 to +70
C
INDEX
AREA
1 2
20
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
--
1.50
--
0.059
b
0.20
0.30
0.008
0.012
c
0.18
0.25
0.007
0.010
D
8.55
8.75
0.337
0.344
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
.635 Basic
.025 Basic
L
0.40
1.27
0.016
0.050
0
8
0
8
aaa
--
0.10
--
0.004
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