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Электронный компонент: ICS8430CY-11T

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8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8432-11 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Frequency
Synthesizer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8432-11 has a selectable TEST_CLK
or crystal inputs. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL
levels. The VCO operates at a frequency range of 200MHz
to 700MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency.
Output frequencies up to 700MHz for FOUT and 350MHz
for FOUT/2 can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics and the multiple frequency outputs of the
ICS8432-11 makes it an ideal clock source for Fiber Channel
1 and 2, and Infiniband applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
Maximum FOUT frequency: 700MHz
Maximum FOUT/2 frequency: 350MHz
VCO range: 200MHz to 700MHz
Parallel interface for programming counter and
VCO frequency multiplier and dividers
Cycle-to-cycle jitter: 25ps (maximum)
RMS period jitter: TBD
3.3V supply voltage
0C to 70C ambient operating temperature
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
HiPerClockSTM
ICS
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_IN
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
nc
V
EE
V
EE
nFOUT
FOUT
V
CCO
nFOUT/2
FOUT/2
V
CC
TEST
XT
AL_OUT
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
ICS8432-11
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
FOUT
nFOUT
FOUT/2
nFOUT/2
TEST
MR
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
nP_LOAD or until a serial event occurs. As a result, the M and
N bits can be hardwired to set the M divider and N output divider
to a specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the paral-
lel input mode. The relationship between the VCO frequency,
the input frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 8
M 28. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output
divider when S_LOAD transitions from LOW-to-HIGH. The
M divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and
N output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes
operation using a 25MHz clock input. Valid PLL loop divider
values for different input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-11 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
ICS8432-11. This input is fed into the phase detector. A 25MHz
clock input provides a 25MHz phase detector reference fre-
quency. The VCO of the PLL operates over a range of 200MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent
to each of the LVPECL output buffers. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8432-11 support two
input modes to program the PLL M divider and N output
divider. The two input operational modes are parallel and
serial. Figure1 shows the timing diagram for each mode. In
parallel mode, the nP_LOAD input is initially LOW. The data
on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the
M divider remains loaded until the next LOW transition on
fVCO = fxtal x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout/2
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
T1
T0
*
NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
fOUT = fVCO = fxtal x M
N
N
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
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8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
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S
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M
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T
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8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
5
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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HARACTERISTICS
,
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CCA
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A
= 0C
TO
70C
NOTE 1: Outputs terminated with 50
to V
CCO
/2. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
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T
S
E
T
5
.
0
V
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
6
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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4C. LVPECL DC C
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,
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CCA
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CCO
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A
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NPUT
F
REQUENCY
C
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CCA
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CCO
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A
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8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
7
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
P
ERIOD
J
ITTER
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
C
YCLE
-
TO
-C
YCLE
J
ITTER
-1.3V 0.165V
tsk(o)
nFOUT
FOUT
nFOUT/2
FOUT/2
O
UPUT
D
UTY
C
YCLE
/O
UTPUT
P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
FOUT,
FOUT/2
nFOUT,
nFOUT/2
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
FOUT,
FOUT/2
nFOUT,
nFOUT/2
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
V
CC
,
V
CCA
, V
CCO
V
EE
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
8
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
S
TORAGE
A
REA
N
ETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below list the common
Table 8. C
OMMON
SAN
S
A
PPLICATIONS
F
REQUENCIES
Table 9. C
ONFIGURATION
D
ETAILS
FOR
SAN
S
A
PPLICATIONS
A
PPLICATIONS
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8
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1
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l
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n
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a
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r
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b
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F
5
2
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2
1
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3
5
0
0
0
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0
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1
1
1
5
2
5
2
.
6
0
1
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1
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2
l
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a
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5
2
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1
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1
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2
1
8
.
2
3
1
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1
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d
n
a
b
i
n
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f
n
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5
2
5
2
1
0
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0
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0
0
0
1
application frequencies as well as the ICS8432-11 configu-
rations used to generate the appropriate frequency.
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
9
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432-11 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
10
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
The schematic of the ICS8432-11 layout example used in this
layout guideline is shown in
Figure 4A. The ICS8432-11 recom-
mended PCB board layout for this example is shown in
Figure
4B. This layout example is used as a general guideline. The lay-
L
AYOUT
G
UIDELINE
F
IGURE
4A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
out in the actual system will depend on the selected component
types, the density of the components, the density of the traces,
and the stacking of the P.C. board.
C16
10u
S_CLOCK
C1
R3
125
C11
0.01u
FO
UT
+
-
IN-
TL2
Zo = 50 Ohm
C15
0.1u
VC
C
IN+
VCCA
FO
UT
N
C2
U1
ICS8432-11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TE
S
T
VC
C
FO
UT
/
2
nF
O
U
T
/
2
VC
C
O
FO
UT
nF
O
U
T
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
XTAL_SEL
T_CLK
X_IN
M4
M3
M2
M1
M0
VC
O_
S
E
L
nP
_
L
OA
D
X_O
U
T
R7
10
S_DATA
VCC
XTAL_SEL
C14
0.1u
REF_IN
VCC=3.3V
VCC
S_LOAD
VC
C
R4
84
TL1
Zo = 50 Ohm
R2
84
R1
125
X1
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
11
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
4B. PCB B
OARD
L
AYOUT
FOR
ICS8432-11
TL1, TL2 are 50 Ohm traces and
equal length
C15
C16
VCC
TL
1
R4
VIA
R7
R1
GND
U1
TL1
R3
X1
Close to the input
pins of the
receiver
C14
PIN 1
T
L1N
VCCA
TL1N
R2
C11
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a spearation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL_IN) and 25 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
12
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 110mA = 381.2mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 381.2mW + 60.4mW = 441.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 10 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.441W * 42.1C/W = 88.6C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
T
ABLE
10. T
HERMAL
R
ESISTANCE
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
13
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
) * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
14
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8432-11 is: 3765
T
ABLE
11.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
15
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
12. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
16
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
13. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.