Document Outline
- General Description
- Features
- Select Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Crystal Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS DC Characteristics
- 3.3V LVDS DC Characteristics
- 3.3V/2.5V LVDS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Typical Phase Noise Plots
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- 3.3V, 2.5V LVDS Driver Termination
- Reliability Information
- Transistor Count
- Package Outline for 24 Lead SOIC
- Package Dimensions for 24 Lead SOIC
- Package Outline for 24 Lead TSSOP
- Package Dimensions for 24 Lead TSSOP
- Ordering Information Table
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
1
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS844256 is a Crystal-to-LVDS Clock
Synthesizer/Fanout Buffer designed for SONET
and Gigabit Ethernet applications and is a
member of the HiperClockSTM family of High
Performance Clock Solutions from ICS. The
output frequency can be set using the frequency select
pins and a 25MHz crystal for Ethernet frequencies, or a
19.44MHz crystal for SONET. The low phase noise charac-
teristics of the ICS844256 make it an ideal clock for these
demanding applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Six LVDS outputs
Crystal oscillator interface
Output frequency range: 62.5MHz to 622.08MHz
Crystal input frequency range: 15.625MHz to 25.5MHz
RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.48ps (typical)
Full 3.3V or 3.3V core, 2.5V output supply mode
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
Q0
ICS844256
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm
body package
M Package
Top View
V
DDO
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
V
DDA
V
DD
FB_SEL
1
2
3
4
5
6
7
8
9
10
11
12
Q3
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
GND
GND
N_SEL0
XTAL_OUT
XTAL_IN
OSC
PLL
Feedback
Divider
Output
Divider
1
0
XTAL_IN
XTAL_OUT
PLL_BYPASS
nQ0
24
23
22
21
20
19
18
17
16
15
14
13
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
FB_SEL
N_SEL1
N_SEL0
Pullup
Pulldown
Pullup
Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
body package
G Package
Top View
S
ELECT
F
UNCTION
T
ABLE
s
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8
4
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
2
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
3
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3. C
RYSTAL
F
UNCTION
T
ABLE
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844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
4
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
24 Lead SOIC
50C/W (0 lfpm)
24 Lead TSSOP
70C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
5
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
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W
/I
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844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
6
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
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W
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NTEGRATED
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844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
7
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
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-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.48ps (typical)
O
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F
REQUENCY
(H
Z
)
N
OISE
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Hz
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Gb Ethernet Filter to raw data
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-100
-110
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-130
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-150
-160
-170
-180
-190
-200
125MHz
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1.875MHz to 20MHz = 0.44ps (typical)
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10
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100M
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
8
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
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ALL
T
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Clock
Outputs
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80%
80%
20%
t
R
t
F
V
SW I N G
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
nQ0:nQ5
Q0:Q5
t
sk(o)
nQx
Qx
nQy
Qy
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
S
KEW
Qx
nQx
3.3V
2.5V
Float GND
+ +
POWER
SUPPLY
SCOPE
LVDS
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
O
FFSET
V
OLTAGE
S
ETUP
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
9
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The ICS844256 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
DD
, V
DDA
and
V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 1
illustrates how a 10
resistor along with a 10
F and a .01F bypass capacitor
should be connected to each V
DDA
pin. The 10
resistor
can also be replaced by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
A
PPLICATION
I
NFORMATION
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844256 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using an 18pF parallel resonant crys-
tal and were chosen to minimize the ppm error.
C1
18p
X1
18pF Parallel Crystal
C2
22p
XTAL_IN
XTAL_OUT
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
10
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
3.3V, 2.5V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 3.
In a 100
differential transmission line environment, LVDS drivers
F
IGURE
3. T
YPICAL
LVDS D
RIVER
T
ERMINATION
require a matched load termination of 100
across near
the receiver input.
I
NPUTS
:
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, we
recommend that there is no trace attached.
2.5V or 3.3V
+
-
VDD
100 Ohm Differential Transmission Line
R1
100
LVDS_Driv er
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
11
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844256 is: 3887
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
S
OIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
12
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
24 L
EAD
SOIC
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
B
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Y
S
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-
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6
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P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
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5
4
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.
0
0
8
a
a
a
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-
0
1
.
0
844256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
13
Integrated
Circuit
Systems, Inc.
ICS844256
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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