8624BY
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 12, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8624 is a high performance, 1-to-5
Differential-to-LVHSTL zero delay buffer and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8624 has two selectable clock input pairs.
The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most
standard differential input levels. The VCO operates at a fre-
quency range of 250MHz to 700MHz. Utilizing one of the
outputs as feedback to the PLL, output frequencies up to
700MHz can be regenerated with zero delay with respect to
the input. Dual reference clock inputs support redundant clock
or multiple reference applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Fully integrated PLL
5 differential LVHSTL outputs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
Static phase offset: 100ps
3.3V core, 1.8V output operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
DDO
Q0
nQ0
GND
GND
FB_IN
nFB_IN
V
DD
V
DDO
nQ4
Q4
GND
GND
V
DDA
PLL_SEL
V
DD
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
ICS8624
HiPerClockSTM
,&6
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
0
1
4, 8
8624BY
www.icst.com/products/hiperclocks.html
REV. B FEBRUARY 12, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
o
b
m
y
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m
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ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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o
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L
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6
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3
=
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I
V
0
=
0
5
1
-
A
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
o
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m
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3
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,
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5
6
4
.
3
=
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=
5
-
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N
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_
B
F
n
,
1
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L
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n
,
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n
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,
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5
6
4
.
3
=
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=
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V
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,
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.
0
V
D
D
5
8
.
0
-
V
V
s
i
x
K
L
C
n
,
x
K
L
C
r
o
f
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g
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t
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t
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p
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t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
1
E
T
O
N
D
D
.
V
3
.
0
+
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
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v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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