Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Description
- Pin Characteristics
- Control Input Function Table
- PLL Bypass Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVHSTL DC Characteristics
- Input Frequency Characteristics
- AC Characteristics
- Parameter Measurement Information
- Output Load Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Cycle-to-Cycle Jitter Diagram
- Phase Jitter & Static Phase Offset Diagram
- Output Rise & Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Layout Guideline
- LVHSTL 0-Delay Buffer Schematic Example
- Power & Grounding
- Clock Traces & Termination
- PCB Board Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVHSTL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8624I is a high performance, 1-to-5
Differential-to-LVHSTL zero delay buffer and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8624I has two selectable clock input pairs.
The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most
standard differential input levels. The VCO operates at a fre-
quency range of 250MHz to 630MHz. Utilizing one of the
outputs as feedback to the PLL, output frequencies up to
630MHz can be regenerated with zero delay with respect to
the input. Dual reference clock inputs support redundant clock
or multiple reference applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Fully integrated PLL
5 differential LVHSTL compatible outputs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 630MHz
Input frequency range: 31.25MHz to 630MHz
VCO range: 250MHz to 630MHz
External feedback for "zero delay" clock regeneration
Cycle-to-cycle jitter: 35ps (maximum)
Output skew: 50ps (maximum)
Static phase offset: 30ps 125ps
3.3V core, 1.8V output operating supply
-40C to 85C ambient operating temperature
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
DDO
Q0
nQ0
GND
GND
FB_IN
nFB_IN
V
DD
V
DDO
nQ4
Q4
GND
GND
V
DDA
PLL_SEL
V
DD
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
ICS8624I
HiPerClockSTM
,&6
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
0
1
4, 8
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
2
T
ABLE
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8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
T
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2. P
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3B. PLL B
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F
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T
ABLE
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
4
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
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p
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L
o
N
0
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
l
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3
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L
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6
4
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3
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V
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5
6
4
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3
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0
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L
P
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V
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6
4
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3
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0
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5
1
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A
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
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DD
= V
DDA
= 3.3V5%, V
DDO
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A
= -40C
TO
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L
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L
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3
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:
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T
O
N
H
I
.
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
4D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
l
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5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
l
o
b
m
y
S
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,
0
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L
C
n
,
0
K
L
C
1
K
L
C
n
,
1
K
L
C
1
=
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S
_
L
L
P
5
2
.
1
3
0
3
6
z
H
M
0
=
L
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S
_
L
L
P
0
3
6
z
H
M
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
6
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
LVHSTL
Qx
nQx
V
DD
, V
DDA
= 3.3V 5%
V
DDO
= 1.8V 0.2V
V
DDO
V
DD
, V
DDA
GND = 0V
D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
nCLK0, nCLK1
CLK0, CLK1
GND
V
DD
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
O
UTPUT
S
KEW
tsk(o)
nQx
Qx
nQy
Qy
Cycle-to-Cycle Jitter
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:nQ4
nQ0:nQ4
P
HASE
J
ITTER
AND
S
TATIC
P
HASE
O
FFSET
t()
V
OH
V
OL
V
OH
V
OL
nCLK0, CLK1
CLK0, nCLK1
nFB_IN
FB_IN
(where
t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
tjit() = t() -- t()
mean
= Phase Jitter
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
8
P
ROPAGATION
D
ELAY
t
PD
nCLK0, nCLK1
CLK0, CLK1
nQ0:nQ4
Q0:Q4
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ4
Q0:Q4
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
S W I N G
8624BYI
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REV. A OCTOBER 8, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
2 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8624I provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1 - P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
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REV. A OCTOBER 8, 2002
10
F
IGURE
3A - ICS8624I LVHSTL Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
L
AYOUT
G
UIDELINE
The schematic of the ICS8624I layout example is shown in
Figure 3A. The ICS8624I recommended PCB board layout for this
example is shown in
Figure 3B. This layout example is used as a general guideline. The layout in the actual system will depend on the
selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board.
C11
0.01u
(U1-16)
CLK_SEL
(U1-17)
Zo = 50 Ohm
SEL1
(U1-32)
R4A
50
DIV_SEL[1:0] = 01
VDD
C4
0.1uF
Zo = 50 Ohm
R9
50
VDD=3.3V
CLK_SEL
R4B
50
C2
0.1uF
RU5
SP
VDDO=1.8V
SEL1
C7
0.1uF
VDDA
R2A
50
C1
0.1uF
RU3
1K
(U1-25)
(155.5 MHz)
VDD
R10
50
Zo = 50 Ohm
RD2
1K
R7
10
C16
10u
SP = Space (i.e. not intstalled)
R2B
50
Zo = 50 Ohm
Bypass capacitor located near the power pins
VDDO
PL
L
_
SEL
RD4
SP
155.5 MHz
SEL0
C6
0.1uF
PLL_SEL
3.3V
RU4
1K
VDD
LVHSTL_input
+
-
VDD
R8
50
(U1-24)
SEL0
RD5
1K
U1
8624
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK2
CLK_SEL
MR
VD
D
nF
B
_
I
N
FB
_
I
N
GN
D
GN
D
nQ
0
Q0
V
DDO
VDDO
nQ1
Q1
nQ2
Q2
nQ3
Q3
VDDO
VD
D
PL
L
_
SEL
V
DDA
GN
D
GN
D
Q4
nQ
4
V
DDO
VDDO
RU2
SP
RD3
SP
(U1-9)
3.3V PECL Driver
C5
0.1uF
8624BYI
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REV. A OCTOBER 8, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
F
IGURE
3B - PCB B
OARD
L
AYOUT
F
OR
ICS8624I
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
C1
Pin 1
50 Ohm
Traces
C11
U1
VDD
C7
C4
C5
VDDO
VDDA
C2
VIA
R7
C16
C6
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
12
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8624I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8624I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 135mA = 467.8mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power
_MAX
(3.465V, with all outputs switching) = 467.8mW + 164mW = 631.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.632W * 42.1C/W = 111.6C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
q
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
8624BYI
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REV. A OCTOBER 8, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1V/50
) * (2V - 1V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
4 - LVHSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 8, 2002
14
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8624I is: 1565
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8624BYI
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REV. A OCTOBER 8, 2002
15
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
0
6
.
1
1
A
5
0
.
0
5
1
.
0
2
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5
3
.
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0
4
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5
4
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b
0
3
.
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7
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.
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4
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c
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0
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C
I
S
A
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C
I
S
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B
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0
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E
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I
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S
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e
C
I
S
A
B
0
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5
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q
0
7
c
c
c
0
1
.
0
T
ABLE
9. P
ACKAGE
D
IMENISIONS
Reference Document: JEDEC Publication 95, MS-026
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
8624BYI
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REV. A OCTOBER 8, 2002
16
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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8624BYI
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REV. A OCTOBER 8, 2002
17
Integrated
Circuit
Systems, Inc.
ICS8624I
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-LVHSTL Z
ERO
D
ELAY
B
UFFER
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