Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- PLL Bypass Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- HSTL DC Characteristics
- Input Frequency Characteristics
- AC Characteristics +/- 5%
- AC Characteristics +/- 10%
- Parameter Measurement Information
- 3.3V Core/1.8V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Cycle-to-Cycle Jitter Diagram
- Phase Jitter & Static Phase Offset Diagram
- Output Rise/Fall Time Diagram
- Output Pulse Width/Period Diagram
- Propagation Delay Diagram
- Application Information
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Differential Clock Input Interface
- Layout Guideline
- LVHSTL Zero Delay Buffer Schematic Example
- Power & Grounding
- Clock Traces & Termination
- PCB Board Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVHSTL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8624BY
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8624 is a high performance, 1-to-5
Differential-to-HSTL zero delay buffer and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8624 has two selectable clock input pairs.
The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most
standard differential input levels. The VCO operates at a fre-
quency range of 250MHz to 700MHz. Utilizing one of the
outputs as feedback to the PLL, output frequencies up to
700MHz can be regenerated with zero delay with respect to
the input. Dual reference clock inputs support redundant clock
or multiple reference applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Fully integrated PLL
5 differential HSTL outputs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
Static phase offset: 100ps
3.3V core, 1.8V output operating supply
0C to 70C ambient operating temperature
Lead-Free package available
Industrial temperature information available upon request
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
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DDO
SEL0
SEL1
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CLK1
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CLK_SEL
MR
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nQ0
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GND
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DD
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DDO
nQ4
Q4
GND
GND
V
DDA
PLL_SEL
V
DD
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
ICS8624
HiPerClockSTM
ICS
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
0
1
4, 8
8624BY
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
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8624BY
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
2. P
IN
C
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YPASS
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8624BY
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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m
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5
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1
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3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
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y
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A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
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D
e
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a
t
l
o
V
y
l
p
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p
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6
.
1
8
.
1
0
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
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S
r
e
w
o
P
0
2
1
A
m
I
A
D
D
t
n
e
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r
u
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y
l
p
p
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S
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n
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5
1
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
d
a
o
L
o
N
0
A
m
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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m
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P
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h
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p
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2
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D
D
3
.
0
+
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V
L
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3
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0
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8
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I
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I
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r
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1
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E
S
,
0
L
E
S
R
M
,
L
E
S
_
K
L
C
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
L
E
S
_
L
L
P
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
,
1
L
E
S
,
0
L
E
S
R
M
,
L
E
S
_
K
L
C
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
L
E
S
_
L
L
P
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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L
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L
C
V
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D
V
=
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V
5
6
4
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3
=
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1
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N
I
_
B
F
n
,
1
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L
C
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0
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L
C
n
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D
D
V
=
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V
5
6
4
.
3
=
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A
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1
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L
C
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
N
I
_
B
F
n
,
1
K
L
C
n
,
0
K
L
C
n
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
P
P
e
g
a
t
l
o
V
t
u
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n
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e
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o
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-
k
a
e
P
1
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0
3
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1
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V
R
M
C
2
,
1
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T
O
N
;
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g
a
t
l
o
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t
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d
o
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n
o
m
m
o
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5
.
0
V
D
D
5
8
.
0
-
V
V
s
i
x
K
L
C
n
,
x
K
L
C
r
o
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e
g
a
t
l
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t
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p
n
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m
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m
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t
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t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
1
E
T
O
N
D
D
.
V
3
.
0
+
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
H
I
.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8624BY
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
T
ABLE
4D. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
l
o
b
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5. I
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F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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1
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z
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M
0
=
L
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P
0
0
7
z
H
M
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V10%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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-
o
t
-
k
a
e
P
6
.
0
1
.
1
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
.
d
n
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o
r
g
o
t
.
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o
i
t
i
d
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o
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n
e
v
i
g
a
t
a
g
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w
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e
g
a
t
l
o
v
t
u
p
t
u
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c
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p
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w
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e
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i
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:
2
E
T
O
N
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
C
YCLE
-
TO
-C
YCLE
J
ITTER
P
HASE
J
ITTER
AND
S
TATIC
P
HASE
O
FFSET
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
OD
t
sk(o)
nQx
nQ
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
HSTL
Qx
nQx
V
CMR
Cross Points
V
PP
GND
CLK0,
CLK1
nCLK0,
nCLK1
V
DD
nQx
Qx
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ4
Q0:Q4
t
PD
V
DD
,
V
DDA
0V
3.3V5% or 10%
V
DDO
1.8V0.2V
O
UTPUT
P
ULSE
W
IDTH
/P
ERIOD
nQ0:nQ4
Q0:Q4
P
ROPAGATION
D
ELAY
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
(where
t
() is any random sample, and
t
()
mean
is the average
of the sampled cycles measured on controlled edges)
t
()
mean
= Static Phase Offset
t()
V
OH
V
OL
V
OH
V
OL
nCLK0,
nCLK1
nFB_IN
FB_IN
t
jit() =
t
() --
t
()
mean
= Phase Jitter
CLK0,
CLK1
Pulse Width
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
GND
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ICS8624
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OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8624 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VDD
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A.
H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
F
IGURE
4A. ICS8624 HSTL Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
L
AYOUT
G
UIDELINE
The schematic of the ICS8624 layout example is shown in
Figure 4A. The ICS8624 recommended PCB board layout for
this example is shown in
Figure 4B. This layout example is
used as a general guideline. The layout in the actual system
C11
0.01u
(U1-16)
CLK_SEL
(U1-17)
Zo = 50 Ohm
SEL1
(U1-32)
R4A
50
DIV_SEL[1:0] = 01
VDD
C4
0.1uF
Zo = 50 Ohm
R9
50
VDD=3.3V
CLK_SEL
R4B
50
C2
0.1uF
RU5
SP
VDDO=1.8V
SEL1
C7
0.1uF
VDDA
R2A
50
C1
0.1uF
RU3
1K
(U1-25)
(155.5 MHz)
VDD
R10
50
Zo = 50 Ohm
RD2
1K
R7
10
C16
10u
SP = Space (i.e. not intstalled)
R2B
50
Zo = 50 Ohm
Bypass capacitor located near the power pins
VDDO
PL
L
_
SEL
RD4
SP
155.5 MHz
SEL0
C6
0.1uF
PLL_SEL
3.3V
RU4
1K
VDD
LVHSTL_input
+
-
VDD
R8
50
(U1-24)
SEL0
RD5
1K
U1
8624
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK2
CLK_SEL
MR
VD
D
nF
B
_I
N
FB
_
I
N
GN
D
GN
D
nQ
0
Q0
V
DDO
VDDO
nQ1
Q1
nQ2
Q2
nQ3
Q3
VDDO
VD
D
PL
L
_
SEL
V
DDA
GN
D
GN
D
Q4
nQ
4
V
DDO
VDDO
RU2
SP
RD3
SP
(U1-9)
3.3V PECL Driver
C5
0.1uF
will depend on the selected component types, the density of
the components, the density of the traces, and the stack up
of the P.C. board.
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
F
IGURE
4B. PCB B
OARD
L
AYOUT
F
OR
ICS8624
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
C1
Pin 1
50 Ohm
Traces
C11
U1
VDD
C7
C4
C5
VDDO
VDDA
C2
VIA
R7
C16
C6
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8624.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8624 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 120mA = 416mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power
_MAX
(3.465V, with all outputs switching) = 416mW + 164mW = 580mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.580W * 42.1C/W = 94.4C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
32-
PIN
LQFP, F
ORCED
C
ONVECTION
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DD_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1V/50
) * (2V - 1V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
5. HSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8624 is: 1565
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EADD
LQFP
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
0
6
.
1
1
A
5
0
.
0
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
7
c
c
c
0
1
.
0
T
ABLE
9. P
ACKAGE
D
IMENISIONS
Reference Document: JEDEC Publication 95, MS-026
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Integrated
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ICS8624
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8624BY
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
16
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