87158AG
www.icst.com/products/hiperclocks.html
REV. B JANUARY 17, 2006
1
Integrated
Circuit
Systems, Inc.
ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
1, 2, 4 C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87158 is a high performance 1-to-6
LVPECL-to-HCSL/LVCMOS Clock Generator
and is a member of the HiPerClockSTM family of
High Performance Clock Solutions from ICS. The
ICS87158 has one differential input (which can
accept LVDS, LVPECL, LVHSTL, SSTL, HCSL), six differential
HCSL output pairs and two complementary LVCMOS/LVTTL
outputs. The six HCSL output pairs can be individually con-
figured for divide-by-1, 2, and 4 or high impedance by use of
select pins. The two complementary LVCMOS/LVTTL outputs
can be configured for divide by 2, divide by 4, high imped-
ance, or driven low for low power operation.
The primary use of the ICS87158 is in Intel
E8870 chipsets
that use Intel
Pentium 4 processors. The ICS87158 converts
the differential clock from the main system clock into HCSL
clocks used by Intel
Pentium 4 processors. However, the
ICS87158 is a highly flexible, general purpose device that
operates up to 600MHz and can be used in any situation where
Differential-to-HCSL translation is required.
F
EATURES
Six HCSL outputs
Two LVCMOS/LVTTL outputs
One Differential LVPECL clock input pair
PCLK, nPCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 600MHz (maximum)
Output skew: 100ps (maximum)
Propagation delay: 4ns (maximum)
3.3V operating supply
0C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
Industrial temperature information available upon request
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
GND
V
DD
V
DD
_R
PCLK
nPCLK
GND_R
V
DD
_M
MREF
nMREF
GND_M
V
DD
GND
V
DD
_L
V
DD
GND_L
SEL_T
MULT_0
MULT_1
V
DD
_L
GND_L
SEL_A
SEL_B
SEL_U
PWR_DWN#
V
DD
GND_H
V
DD
_H
HOST_P1
HOST_N1
GND_H
HOST_P2
HOST_N2
V
DD
_H
HOST_P3
HOST_N3
GND_H
HOST_P4
HOST_N4
V
DD
_H
HOST_P5
HOST_N5
GND_H
HOST_P6
HOST_N6
V
DD
_H
IREF
GND_I
V
DD
_I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Lead TSSOP
6.1mm x 12.5mm x .92mm body package
G Package
Top View
48-Lead SSOP
7.5mm x 15.9mm x 2.3mm body package
F Package
Top View
V
DD
HOST_P1
HOST_N1
GND_H
V
DD
HOST_P6
HOST_N6
GND_H
V
DD
HOST_P2
HOST_N2
GND_H
V
DD
HOST_P3
HOST_N3
GND_H
V
DD
HOST_P4
HOST_N4
GND_H
V
DD
HOST_P5
HOST_N5
GND_H
V
DD
MREF
nMREF
GND_H
CURRENT
ADJUST
1,2,4
MULT_0
MULT_1
IREF
PWR_DWN#
SEL_T
PCLK
nPCLK
SEL_A
SEL_B
SEL_U
DIVIDER
CONTROL
-
+
1,2,4
2,4
87158AG
www.icst.com/products/hiperclocks.html
REV. B JANUARY 17, 2006
4
Integrated
Circuit
Systems, Inc.
ICS87158
1-
TO
-6, LVPECL-
TO
-HCSL/LVCMOS
1, 2, 4 C
LOCK
G
ENERATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
85C
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ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
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T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
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3
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3
"
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
48 Lead TSSOP
58.3C/W (0 lfpm)
48 Lead SSOP
52.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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