8752CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8752I
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
V
DDO
V
DDO
QA3
QA2
GND
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
GND
FB_IN
V
DDO
QA1
QA0
GND
CLK1
V
DD
V
DDA
CLK_SEL
V
DDO
QB2
QB3
GND
GND
nc
PLL_SEL
V
DD
ICS8752I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
2
4
6
8
12
PLL
PHASE
DETECTOR
PLL_SEL
FB_IN
CLK0
CLK1
CLK_SEL
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
MR/nOE
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
0
1
1
0
00
01
10
11
00
01
10
11
VCO
G
ENERAL
D
ESCRIPTION
The ICS8752I is a low voltage, low skew
LVCMOS clock generator and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. With output fre-
quencies up to 240MHz, the ICS8752I is tar-
geted for high performance clock applications. Along with a
fully integrated PLL, the ICS8752I contains frequency
configurable outputs and an external feedback input for re-
generating clocks with "zero delay".
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which reference
clock is used. The output divider values of Bank A and B are
controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752I are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
F
EATURES
Fully integrated PLL
8 LVCMOS outputs, 7
typical output impedance
Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
Input/Output frequency range: 18.33MHz to 240MHz
at V
CC
= 3.3V 5%
VCO range: 220MHz to 480MHz
External feedback for "zero delay" clock regeneration
Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
Output skew: 100ps (maximum)
Bank skew: 55ps (maximum)
3.3V or 2.5V supply voltage
-40C to 85C ambient operating temperature
Functionally compatible with MPC952 in some applications
HiPerClockSTM
,&6
8752CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8752I
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
5B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
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